References
[1]. Andra, K., Chakrabarti, C., & Acharya, T. (2002). A VLSI architecture for lifting-based forward and inverse wavelet transform. IEEE Transactions on Signal Processing, 50(4), 966-977.
[2]. Acharya, T., & Chakrabarti, C. (2006). A survey on lifting-based discrete wavelet transform architectures. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 42(3), 321-339.
[3]. Barua, S., Carletta, J. E., Kotteri, K. A., & Bell, A. E. (2004, April). An efficient architecture for lifting-based two-dimensional discrete wavelet transforms. In Proceedings of the 14th ACM Great Lakes Symposium on VLSI (pp. 61-66). ACM.
[4]. Bhanu, U. N., & Chilambuchelvan, A. (2012). A detailed survey on VLSI architectures for lifting based DWT for efficient hardware implementation. International Journal of VLSI Design & Communication Systems, 3(2), 143-164.
[5]. Chakrabarti, C., Vishwanath, M., & Owens, R. M. (1996). Architectures for wavelet transforms: A survey. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 14(2), 171-192.
[6]. Chakrabarti, C., & Vishwanath, M. (1995). Efficient realizations of the discrete and continuous wavelet transforms: From single chip implementations to mappings on SIMD array computers. IEEE Transactions on Signal Processing, 43(3), 759-771.
[7]. Chrysafis, C., & Ortega, A. (2000). Line-based, reduced memory, wavelet image compression. IEEE Transactions on Image Processing, 9(3), 378-389.
[8]. Chrysafis, C., & Ortega. A, (1998). Line-based reduced memory wavelet image compression. In Proc. IEEE Data Compression Conf. (pp. 308-407).
[9]. Chandra, B. & Sharma, M. (2016). A review of VLSI Architecture for DWT. International Journal of Science Technology & Engineering (IJSTE), 3(3), 179-185.
[10]. Daubechies, I., & Sweldens, W. (1998). Factoring wavelet transforms into lifting steps. Journal of Fourier Analysis and Applications, 4(3), 247-269.
[11]. Huang, C. T., Tseng, P. C., & Chen, L. G. (2004). Flipping structure: An efficient VLSI architecture for liftingbased discrete wavelet transform. IEEE Transactions on Signal Processing, 52(4), 1080-1089.
[12]. Jiang, W., & Ortega, A. (2001). Lifting factorizationbased discrete wavelet transform architecture design. IEEE Transactions on Circuits and Systems for Video Technology, 11(5), 651-657.
[13]. Jou, J. M., Shiau, Y. H., & Liu, C. C. (2001, May). Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme. In Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on (Vol. 2, pp. 529-532). IEEE.
[14]. Liao, H., Mandal, M. K., & Cockburn, B. F. (2004). Efficient architectures for 1-D and 2-D lifting-based wavelet transforms. IEEE Transactions on Signal Processing, 52(5), 1315-1326.
[15]. Mallat, S. G. (1989). A theory for multi resolution signal decomposition: The wavelet representation. IEEE Transactions on Pattern Analysis and Machine Intelligence, 11(7), 674-693.
[16]. Parhi, K. K. (1991). A systematic approach for design of digit-serial signal processing architectures. IEEE Transactions on Circuits and Systems, 38(4), 358-375.
[17]. Parhi, K. K. (1992). Systematic synthesis of DSP data format converters using life-time analysis and forwardbackward register allocation. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 39(7), 423-440.
[18]. Parhi, K. K., & Nishitani, T. (1993a). VLSI architectures for discrete wavelet transforms. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1(2), 191-202.
[19]. Parhi, K. K., & Nishitani, T. (1993b, May). Folded VLSI architectures for discrete wavelet transforms. In Circuits and Systems, 1993., ISCAS'93, 1993 IEEE International Symposium on (pp. 1734-1737). IEEE.
[20]. Ritu, & Sharma, P. (2014). Wavelet based Image Compression. International Journal of Emerging Trends in Science and Technology (IJETST), 1(8), 1267-1272.
[21]. Sarala. J & Sivanantham. E, (2014). Design of multilevel 2D DWT for image processing applications, International Journal of Computing Communication and Information System (IJCCIS), 6(1), 1-6.
[22]. Sweldens, W. (1996). The lifting scheme: A custom- design construction of biorthogonal wavelets. Applied and Computational Harmonic Analysis, 3(2), 186-200.
[23]. Senthilkumar, S., Radhakrishnan, D. R., & Krishnan, M. G. (2010). A survey on VLSI architectures of Lifting based 2D Discrete Wavelet Transform. International Journal of Advanced Computer Technology (IJACT), 3(6), 5-13.
[24]. Sifuzzaman, M., Islam, M. R., & Ali, M. Z. (2009). Application of wavelet transform and its advantages compared to Fourier transform. Journal of Physical Sciences, 13, 121-134.
[25]. Sowjanya, D., Srinivas, K. N. H., & Ganapathi, P. V. (2012). FPGA implementation of efficient VLSI architecture for fixed point 1-D DWT using lifting scheme. Int. J. of VLSI Design & Communication Systems, 3(4), 37- 48.
[26]. Srinivasarao, B. K. N., & Chakrabarti, I. (2015). High speed VLSI architecture for 3D DWT. 2016 International Symposium on VLSI Design, Automation and Test (VLSIDAT) (pp. 1-14).
[27]. Vishwanath, M., Owens, R. M., & Irwin, M. J. (1995). VLSI architectures for the discrete wavelet transform. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 42(5), 305-316.
[28]. Yu, C., & Chen, S. J. (1997). VLSI implementation of 2- D discrete wavelet transform for real-time video signal processing. IEEE Transactions on Consumer Electronics, 43(4), 1270-1279.