References
[1]. Cho, T. B., & Gray, P. R. (1994, May). A 10-bit, 20-MS/s,
35-mW pipeline A/D converter. In Custom Integrated
Circuits Conference, 1994., Proceedings of the IEEE 1994
(pp. 499-502). IEEE.
[2]. Kaess, F., Kanan, R., Hochet, B., & Declercq, M. (1997,
June). New encoding scheme for high-speed flash ADCs.
In Circuits and Systems, 1997. ISCAS'97, Proceedings of
1997 IEEE International Symposium on (Vol. 1, pp. 5-8).
IEEE.
[3]. Kanan, R., Kaess, F., & Declercq, M. (1999, July). A 640
mW high accuracy 8-bit 1 GHz flash ADC encoder. In
Circuits and Systems, 1999. ISCAS'99. Proceedings of the
1999 IEEE International Symposium on (Vol. 2, pp. 420-
423). IEEE.
[4]. Lee, D., Yoo, J., Choi, K., & Ghaznavi, J. (2002,
August). Fat tree encoder design for ultra-high speed flash
A/D converters. In Circuits and Systems, 2002. MWSCAS- 2002. The 2002 45 Midwest Symposium on (Vol.2, pp.87-
90). IEEE.
[5]. Sail, E., & Vesterbacka, M. (2004, November). A
multiplexer based decoder for flash analog-to-digital
converters. In TENCON 2004. 2004 IEEE Region 10
Conference (Vol. 500, pp. 250-253). IEEE.
[6]. Teichmann, P. (2012). Fundamentals of adiabatic
logic. In Adiabatic Logic (pp. 5-22). Springer, Dordrecht.
[7]. Upadhyay, S., Nagaria, R. K., & Mishra, R. A. (2013).
Low-power adiabatic computing with improved
quasistatic energy recovery logic. VLSI Design, 2013.
[8]. Yoo, J. (2003). A TIQ based flash A/D Converter for
Systemon-Chip Applications (Doctoral Dissertation, The
Pennsylvania State University).
[9]. Yoo, J., Choi, K., & Tangel, A. (2001, May). A 1-GSPS
CMOS flash A/D converter for system-on-chip
applications. In VLSI 2001. Proceedings. IEEE Computer
Society Workshop on (pp. 135-139). IEEE.
