References
[1]. Ansari, H. K., & Farooqi, A. S. (2012). Design of high speed UART for programming FPGA. International Journal of Engineering and Computer Science,1(1), 28-36.
[2]. Fang, Y. Y., & Chen, X. J. (2011, May). Design and simulation of UART serial communication module based on VHDL. In Intelligent Systems and Applications (ISA), 2011 3rd International Workshop on (pp. 1-4). IEEE.
[3]. Kedar, S. (2014). Vhdl Implementation of Universal Asynchronous Receiver Transmitter, Proceedings of 11th IRF International Conference, IEEE.
[4]. Kumar, M. V., & Angadi, S. (2012). Study of UART Transmitter in Microcontroller. International Journal of Engineering and Advanced Technology (IJEAT), 2(2), 155- 158.
[5]. Laddha, M. N. R., & Thakare, A. P. (2013a). Implementation of serial communication using UART with configurable baud rate. IJRITCC, 1(4), 263-268.
[6]. Laddha, N. R., & Thakare, A. P. (2013b). A review on serial communication by UART. International Journal of Advanced Research in Computer Science and Software Engineering, 3(1), 366-369.
[7]. Longadge, R., Mahindra, M., & Dahake, V. (2015). Design and implementation of UART. International Journal of Advanced Research in Computer and Communication Engineering, 4(5), 315-317.
[8]. Moussa, S., Abdel Razik, A. M., Dahmane, A. O., & Hamam, H. (2013). FPGA implementation platform for MIMO-OFDM based on UART. J. Emerg. Trend Comput. Inf. Sci., 4(4), 367-371.
[9]. Patel, N., Patel, V., & Patel, V. (2012, May). VHDL implementation of UART with status register. In Communication Systems and Network Technologies (CSNT), 2012 International Conference on (pp. 750-754). IEEE.
[10]. Rawat, S. S., & Ramola, V. (2015). UART design using FIFO ram and LCR circuit with BIST capability at different baud rate. International Journal of Engineering Development and Research. 2015 IJEDR, 3(3), 1-4.
[11]. Shrivastava, P., & Sharma, S. (2014). Design and simulation of 16 bit UART Serial Communication Module based on VHDL. International Journal of Emerging Technology and Advanced Engineering, 4(4), 73-78.
[12]. Yu, S., Yi, L., Chen, W., & Wen, Z. (2007, May). Implementation of a Multi-channel UART controller based on FIFO Technique and FPGA. In Industrial Electronics and Applications, 2007. ICIEA 2007. 2nd IEEE Conference on (pp. 2633-2638). IEEE.
[13]. Yuan, H., Yang, J., & Pan, P. (2010, June). Optimized design of UART IP soft core based on DMA mode. In Industrial Electronics and Applications (ICIEA), 2010 the 5th IEEE Conference on (pp. 1907-1910). IEEE.