In this paper, in orderto meet the needs of Wireless Access in Vehicular Environment applications, Analog-to-Digital converter with 10 bit 40 MS/s (Mega Samples per second) has been introduced. The ADC planned here is to be compelled to be operates at high varying temperatures under the given constraints. To implement the system, the design was changed by reducing the gratuitous building blocks that the area unit provides within the existing design. The non essential building blocks area unit comprises reference drivers, Sample and Hold Applications (SHA),, level shifters, etc. In the planned design there is a tendency to take away these building blocks and introduce the internal signal amplification technique. This amplification technique extends the effective signal by varying each multiplying data converter and flash ADC, in addition to that, the error correction vary. The new clock generation circuit for a SHA-less pipelined ADC removes the requirement of a better frequency external clock. The prototype ADC was fabricated in a 32- nm CMOS process. The design is developed by using the backend tool HSPICE Design suite and Virtex6 FPGA for hardware Prototyping Environment. The Design summary and simulation waveforms shows that the proposed Architecture consumes low power and work with high performance.