i-manager Publications

Effect of Halo Implant and Threshold Implant on Sub-Threshold Current and Substrate Current of MOSFET

Nitin Sachdeva*, Munish Vashishath**, P.K.Bansal***

* Assistant Professor, Department of Electronics Engineering, YMCAUST, Faridabad, India.

** Chairman and Professor, Department of Electronics Engineering, YMCAUST, Faridabad, India.

*** Professor, Department of Electronics Engineering, MMIT, Malout, India.

Periodicity:July - December'2017
DOI : https://doi.org/10.26634/jes.6.1.13893

Abstract

In this paper, the concentration of halo implant and threshold implant has been varied to estimate the sub-threshold leakage current and substrate current of the MOSFET. A lightly doped NMOS has been designed having channel length of 40 nm in Athena and simulated in Atlas of Silvaco TCAD tool. After simulation results, it has been observed that as the threshold implant and halo implant concentrations are increased, there is a decrease in both off-state sub-threshold leakage and substrate current as required for an ideal MOSFET. Other parameters like ON current, DIBL, and threshold voltage have also been estimated.

Keywords

MOSFET, SILVACO, Athena, Atlas ,TCAD.

How to Cite this Article?

Sachdeva, N., Vashishath, M., and Bansal, P. K. (2017). Effect of Halo Implant and Threshold Implant on Sub-Threshold Current and Substrate Current of MOSFET. i-manager's Journal on Embedded Systems, 6(1), 23-29. https://doi.org/10.26634/jes.6.1.13893

References

[1]. Berkeley Predictive Technology Model, UC Berkeley Device Group. Retrieved from http://ptm.asu.edu/

[2]. Dwivedi, A. K., Tyagi, S., & Islam, A. (2015). Threshold voltage extraction and its reliance on device parameters@ 16-nm process technology. In Computer, Communication, Control and Information Technology (C3IT) (pp. 1-6).

[3]. ITRS. (2003). International Technology Roadmap for Semiconductor. Retrieved from https://www.semi conductors.org/main/2003_international_technology_roa dmap_for_semiconductors_itrs/

[4]. ITRS. (2007). International Technology Roadmap for Semiconductor. Retrieved from http://www.itrs2.net/

[5]. Kang, S. M., & Leblebici, Y. (2003). CMOS Digital Integrated Circuits. Tata McGraw-Hill Education.

[6]. Ortiz-Conde, A., García-Sánchez, F. J., Muci, J., Barrios, A. T., Liou, J. J., & Ho, C. S. (2013). Revisiting MOSFET threshold voltage extraction methods. Microelectronics Reliability, 53(1), 90-104.

[7]. Osthaug, J., Fjeldly, T. A., & Iniguez, B. (2004). Closedform 2D modeling of sub-100 nm MOSFETs in the subthreshold regime. Journal of Telecommunications and Information Technology, 1, 70-79.

[8]. Sachdeva, N., Vashishath, M., & Bansal, P. K. (2017a). Effect of Various Parameters on Threshold Voltage of Virtually Fabricated Lightly Doped PMOS Device. Journal of VLSI Design Tools & Technology, 7(3), 13-20.

[9]. Sachdeva, N., Vashishath, M., & Bansal, P. K. (2017b). Analytical Modeling and Simulation of OFF-State Leakage Current for Lightly Doped MOSFETs. Journal of Nano-and Electronic Physics, 9(6), 6009-1.

[10]. Silvaco International. (1995). Silvaco: Virtual Wafer Fab. Retrieved from http://www.silvaco.com/products/ vwf/vwf.html

[11]. Zabeli, M., Caka, N., Limani, M., & Kabashi, Q. (2008). The threshold voltage of MOSFET and its influence on digital circuits. Recent Advances in Systems, Communications & Computers (pp. 266-271). WSEAS.

If you have access to this article please login to view the article or kindly login to purchase the article

Single Article

	North Americas,UK, Middle East,Europe		India	Rest of world
	USD	EUR	INR	USD-ROW
Online	15	15

ADD TO CART

Options for accessing this content:

If you would like institutional access to this content, please recommend the title to your librarian.
If you already have i-manager's user account: Login above and proceed to purchase the article.
New Users: Please register, then proceed to purchase the article.