An Exposition on Rescaling of Cache

Mayuri Chawla*, Sanjay M. Asutkar**, Vijay Chourasia***
* Assistant Professor, Department of Electronics & Telecommunication Engineering, Jhulelal Institute of Technology, Nagpur, India.
** Associate Professor, Department of Electronics & Telecommunication Engineering, MIET, Gondia, India.
*** Assistant Professor, Department of Electronics & Telecommunication Engineering, MIET, Gondia, India.
Periodicity:March - May'2017
DOI : https://doi.org/10.26634/jcom.5.1.13794

Abstract

Over the years, as the dependence on the computer based system has been on the rise and the researchers have made inroads in the ways in which the performance of the system gets improved with the time. The authors have reviewed and analyzed the different schemes or methodologies which have been proposed by different researchers concerned with improving the performance of the hardware with intent of developing a new caching technique that will present the cache dynamically as needed and shuts the processor cache to save the power. The review has been carried to track the development that has been carried out over the years in the domain of cache utilization and its improvisations. The review includes research papers, publications, web sources, and other available literature with an eye towards providing a comprehensive comparative analysis. Thus they put forward the insights gained from the review.

Keywords

Cache, Resizing, Miss Ratio, Energy Estimation

How to Cite this Article?

Chawla, M., Asutkar, S., and Chourasia, V. (2017). An Exposition on Rescaling of Cache. i-manager’s Journal on Computer Science, 5(1), 22-37. https://doi.org/10.26634/jcom.5.1.13794

References

[1]. Asaduzzaman, A., Rani, M., & Sibai, F. N. (2010, December). On the design of low-power cache memories for homogeneous multi-core processors. In Microelectronics (ICM), 2010 International Conference on (pp. 387-390). IEEE.
[2]. Bae, Y. C., Park, J. Y., Rhee, S. J., Ko, S. B., Jeong, Y., Noh, K. S. et al. (2012, February). A 1.2 V 30nm 1.6 Gb/s/pin 4GB LPDDR3 SDRAM with input skew calibration and enhanced control scheme. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International (pp. 44-46). IEEE.
[3]. Baghel, V. S., & Akashe, S. (2015, February). Low power memristor based 7T SRAM using MTCMOS technique. In Advanced Computing & Communication Technologies (ACCT), 2015 Fifth International Conference on (pp. 222-226). IEEE.
[4]. Bhattacharjee, A., Contreras, G., & Martonosi, M. (2008, August). Full-system chip multiprocessor power evaluations using FPGA-based emulation. In Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on (pp. 335-340). IEEE.
[5]. Calagos, M., & Chu, Y. (2016, July). Buffer-controlled c a c h e f o r l o w- p o w e r m u l t i c o r e s y s t e m s. I n Communications and Electronics (ICCE), 2016 IEEE Sixth International Conference on (pp. 147-152). IEEE.
[6]. Chauhan, R., Vyavahare, P., & Kothamasu, S. (2015, March). Fail-safe I/O to control RESET# pin of DDR3 SDRAM and achieve ultra-low system power. In Quality Electronic th Design (ISQED), 2015 16 International Symposium on (pp. 357-360). IEEE.
[7]. Chen, X., & Jha, N. K. (2016). A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(5), 1649-1662.
[8]. Choi, W., & Park, J. (2016). A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design. IEEE Transactions on Circuits and Systems I: Regular Papers, 63(8), 1164-1175.
[9]. Gaillardon, P. E., Tang, X., Sandrini, J., Thammasack, M., Omam, S. R., Sacchetto, D., et al. (2015, March). An ultra-low-power FPGA based on monolithically integrated RRAMs. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (pp. 1203-1208). EDA Consortium.
[10]. Imani, M., Patil, S., & Rosing, T. (2016, March). Low power data-aware STT-RAM based hybrid cache architecture. In Quality Electronic Design (ISQED), 2016 th 17 International Symposium on (pp. 88-94). IEEE.
[11]. Imani, M., Rahimi, A., Kim, Y., & Rosing, T. (2016, August). A low-power hybrid magnetic cache architecture exploiting narrow-width values. In Non- Volatile Memory Systems and Applications Symposium th (NVMSA), 2016 5 (pp. 1-6). IEEE.
[12]. Ito, M., & Ohara, M. (2016, April). A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm. In Low-Power and High- Speed Chips (COOL CHIPS XIX), 2016 IEEE Symposium in (pp. 1-3). IEEE.
[13]. Jang, S. J., Chung, M. K., Kim, J., & Kyung, C. M. (2007, May). Cache miss-aware dynamic stack allocation. In Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on (pp. 3494-3497). IEEE.
[14]. Jeong, H., Park, J., Oh, T. W., Rim, W., Song, T., Kim, G., et al. (2016). Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM. IEEE Transactions on Circuits and Systems II: Express Briefs, 63(11), 1059-1063.
[15]. Kamoun, N., Bossuet, L., & Ghazel, A. (2008, December). SRAM-FPGA implementation of masked SBox based DPA countermeasure for AES. In Design and Test rd Workshop, 2008. IDT 2008. 3 International (pp. 74-77). IEEE.
[16]. Kaushik, C. S. H., Vanjarlapati, R. R., Krishna, V. M., Gautam, T., & Elamaran, V. (2014, March). VLSI design of low power SRAM architectures for FPGAs. In Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on (pp. 1-4). IEEE.
[17]. Kim, J. P., Yang, W., & Tan, H. Y. (2003). A low-power 256-MB SDRAM with an on-chip thermometer and biased reference line sensing scheme. IEEE Journal of Solid-State Circuits, 38(2), 329-337.
[18]. Kim, S. H., Lee, W. O., Kim, J. H., Lee, S. S., Hwang, S. Y., Kim, C. I., et al. (2007, November). A low power and highly reliable 400Mbps mobile DDR SDRAM with on-chip distributed ECC. In Solid-State Circuits Conference, 2007. ASSCC'07. IEEE Asian (pp. 34-37). IEEE.
[19]. Lee, J. C., Jin, S. H., Kim, D. S., Ku, Y. J., Kim, C., Park, B. K., et al. (2011, November). A low-power small-area open loop digital DLL for 2.2 Gb/s/pin 2Gb DDR3 SDRAM. In Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian (pp. 157-160). IEEE.
[20]. Leming, G. V., & Nepal, K. (2009, August). Low-Power FPGA routing switches using adaptive body biasing technique. In Circuits and Systems, 2009. MWSCAS'09. nd 52 IEEE International Midwest Symposium on (pp. 447- 450). IEEE.
[21]. Li, C., Qiao, F., & Yang, H. (2010, June). Low power cache architecture with security mechanism. In nd Education Technology and Computer (ICETC), 2010 2 International Conference on (Vol. 1, pp. V1-573). IEEE.
[22]. Lin, T. J., Zhang, W., & Jha, N. K. (2012). SRAM-based NATURE: A dynamically reconfigurable FPGA based on 10T low-power SRAMs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(11), 2151-2156.
[23]. Liu, Z. Y., Shih, H. C., Lin, B. Y., & Wu, C. W. (2017). Controller Architecture for Low-Power, Low-Latency DRAM with Built-in Cache. IEEE Design & Test, 34(2), 69-78.
[24]. Miura, S., Ayukawa, K., & Watanabe, T. (2001, August). A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. In Proceedings of the 2001 International Symposium on Low Power Electronics and Design (pp. 358-363). ACM.
[25]. Oguntebi, T., Hong, S., Casper, J., Bronson, N., Kozyrakis, C., & Olukotun, K. (2010, May). FARM: A p r o t o t y p i n g e n v i r o nme n t f o r t i g h t l y- c o u p l e d, heterogeneous architectures. In Field-Programmable th Custom Computing Machines (FCCM), 2010 18 IEEE Annual International Symposium on (pp. 221-228). IEEE.
[26]. Peng, M., & Liu, X. (2013, June). Adaptive Rapid Reconfigurable Algorithm for Low Power Cache. In Computational and Information Sciences (ICCIS), 2013 Fifth International Conference on (pp. 203-206). IEEE.
[27]. Ramaswamy, S., & Yalamanchili, S. (2007). Improving cache efficiency via resizing & plus; th remapping. In Proceedings of the 25 International Conference on Computer Design (pp. 47-54). IEEE.
[28]. Ritzenthaler, R., Schram, T., Bury, E., Spessot, A., Caillat, C., Srividya, V., et al. (2013). Low-power DRAMcompatible replacement gate high-k/metal gate stacks. Solid-State Electronics, 84, 22-27.
[29]. Sampson, J., Arora, M., Goulding-Hotta, N., Venkatesh, G., Babb, J., Bhatt, V., et al. (2011, September). An evaluation of selective depipelining for F P G A- b a s e d e n e r g y- r e d u c i n g i r r e g u l a r c o d e coprocessors. In Field Programmable Logic and Applications (FPL), 2011 International Conference on (pp. 24-29). IEEE.
[30]. Seyedi, A., Armejach, A., Cristal, A., Unsal, O. S., & Valero, M. (2012, November). Novel SRAM bias control circuits for a low power L1 data cache. In NORCHIP, 2012 (pp. 1-6). IEEE.
[31]. Simon, W., Yüzügüler, A. C., Ibrahim, A., Angiolini, F., Arditi, M., Thiran, J. P., et al. (2016, August). Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer. In Field Programmable Logic and th Applications (FPL), 2016 26 International Conference on (pp. 1-2). IEEE.
[32]. Sterpone, L., Carro, L., Matos, D., Wong, S., & Fakhar, F. (2011, March). A new reconfigurable clock-gating technique for low power SRAM-based FPGAs. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011 (pp. 1-6). IEEE.
[33]. Sutar, S., Raha, A., & Raghunathan, V. (2016, October). D-PUF: an intrinsically reconfigurable dram puf for device authentication in embedded systems. In Compliers, Architectures, and Synthesis of Embedded Systems (CASES), 2016 International Conference on (pp. 1-10). IEEE.
[34]. Suzuki, D., & Hanyu, T. (2016, August). A low-power MTJ-based nonvolatile FPGA using self-terminated logicin- memory structure. In Field Programmable Logic and th Applications (FPL), 2016 26 International Conference on (pp. 1-4). IEEE.
[35]. Tang, X., Gaillardon, P. E., & De Micheli, G. (2014, December). A high-performance low-power near-Vt RRAM-based FPGA. In Field-Programmable Technology (FPT), 2014 International Conference on (pp. 207-214). IEEE.
[36]. Wang, Y., Bhattacharya, U., Hamzaoglu, F., Kolar, P., Ng, Y. G., Wei, L., et al. (2010). A 4.0 GHz 291 Mb voltagescalable SRAM design in a 32 nm high-k+ metal-gate CMOS technology with integrated power management. IEEE Journal of Solid-State Circuits, 45(1), 103-110.
[37]. Xu, C., Zhang, G., & Hao, S. (2009, July). Fast wayprediction instruction cache for energy efficiency and high performance. In Networking, Architecture, and Storage, 2009. NAS 2009. IEEE International Conference on (pp. 235-238). IEEE.
[38]. Yoshimi, M., Kudo, R., Oge, Y., Terada, Y., Irie, H., & Yoshinaga, T. (2014, September). An FPGA-based tightly coupled accelerator for data-intensive applications. In Embedded Multicore/Manycore SoCs (MCSoC), 2014 th IEEE 8 International Symposium on (pp. 289-296). IEEE.
[39]. Zaitsu, K., Tatsumura, K., Matsumoto, M., Oda, M., Fujita, S., & Yasuda, S. (2014, June). Flash-based nonvolatile programmable switch for low-power and high-speed FPGA by adjacent integration of MONOS/logic and novel programming scheme. In VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on (pp. 1-2). IEEE.
[40]. Zhang, T., Chen, K., Xu, C., Sun, G., Wang, T., & Xie, Y. (2014, June). Half-DRAM: A high-bandwidth and lowpower DRAM architecture from the rethinking of finegrained activation. In Computer Architecture (ISCA), st 2014 ACM/IEEE 41 International Symposium on (pp. 349- 360). IEEE.
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