A Novel Output Vector Monitoring Online Concurrent BIST Architecture For VLSI Circuits

Philemon P. Daniel*, Rajeevan Chandel**
* Assistant Professor, National Institute of Technology, Hamirpur.
** Associate Professor, National Institute of Technology, Hamirpur.
Periodicity:December - February'2011
DOI : https://doi.org/10.26634/jele.1.2.1368

Abstract

Online concurrent testing of VLSI circuits continues to be a challenge because of the need to test circuits during their normal operation. As offline test techniques and online non-concurrent BISTs cannot be used, new techniques like input vector monitoring concurrent BIST schemes were attempted. But the best of the techniques suffer from major limitations like extremely high concurrent test latency, exponential area overhead, limited fault models and therefore are not a viable solution. In this paper a novel output vector monitoring concurrent BIST scheme is presented. The proposed scheme uses the advantage of an embedded system application and tests only for faults that can occur for the currently loaded application using the run time vectors. This method brings down concurrent test latency to a small fraction, tests for all at-speed fault models, uses a scalable BIST architecture without a noticeable increase in overhead. It eliminates aliasing completely because of double vector compactors. The BIST can also be used for offline concurrent tests which can provide additional coverage to a SBST method. The applicability is validated by implementing the scheme for ALU and decoder in OC8051. To the best of our knowledge the concurrent online BIST using output vector monitoring which works for both online and offline tests is presented for the first time in the open literature.

Keywords

Online Testing, Concurrent Test, Offline Testing, Built-In-Self-Test, Output Vector Monitoring

How to Cite this Article?

Philemon Daniel and Rajeevan Chandel (2011). A Novel Output Vector Monitoring Online Concurrent BIST Architecture for VLSI Circuits. i-manager’s Journal on Electronics Engineering, 1(2), 22-29. https://doi.org/10.26634/jele.1.2.1368

References

[1]. J. Srinivasan, S.V. Adve, P. Bose, & J.A. Rivers, [2005]. “Exploiting structural duplication for lifetime reliability enhancement,” in Proc. 32nd Int. Symp. Comput. Arch. (ISCA), pp. 520–531.
[2]. H. Al-Asaad & M. Shringi, [2000]. “On-Line Built-In Self- Test for Operational Faults,” Proc. Systems Readiness Technology Conf., pp. 168-174.
[3]. M. Abramovici, M. Breuer, & A. Friedman, [1990]. Digital Systems Testing and Testable Design. Computer Science Press.
[4]. A. Mahmood & E. McCluskey, [1988]. “Concurrent error detection using watchdog processors-A survey”, IEEE Transactions on Computers, Vol.C-37, pp. 160-174, February.
[5]. B.W. Johnson, [1989]. Design and Analysis of Fault Tolerant Digital Systems, Addison-Wesley, Reading, Massachusetts.
[6]. K.K. Saluja, R. Sharma, & C.R. Kime, [1988]. “A Concurrent Testing Technique for Digital Circuits,” IEEE Trans. Computer-Aided Design, Vol. 7, No. 12, pp. 1259, Dec.
[7]. K.K. Saluja, R. Sharma, and C.R. Kime, [1987]. “Concurrent Comparative Testing Using BIST Resources,” Proc. Int'l Conf. Computer Aided Design, pp. 336-339, Nov.
[8]. K.K. Saluja, R. Sharma, and C.R. Kime, [1986]. “Concurrent Comparative Built-In Testing of Digital Circuits,” Technical Report ECE-8711, Dept. of Electrical and Computer Eng., Univ. of Wisconsin.
[9]. I. Voyiatzis and C. Halatsis, [2005]. “A Low Cost Concurrent BIST Scheme for Increased Dependability,” IEEE Trans. Dependable and Secure Computing, Vol. 2, No. 2, Apr.-June.
[10]. I. Voyiatzis, A. Paschalis, D. Gizopoulos, N. Kranitis, and C.Halatsis, [2005]. “A Concurrent Built-In Self Test Architecture Based on a Self-Testing RAM,” IEEE Trans. Reliability, Vol. 54, No. 1, pp. 69-78, Mar.
[11]. R. Sharma and K.K. Saluja, [1993]. “Theory, Analysis and Implementation of an On-Line BIST Technique,” VLSI Design, Vol. 1, No. 1, pp. 9-22.
[12]. Voyiatzis, I. Paschalis, A. Gizopoulos, D. Halatsis, C. Makri, F.S. Hatzimihail, M., [2008]. "An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set," Computers, IEEE Transactions on, Vol.57, No.8, pp.1012-1022, Aug.
[13]. J. Rajski and J. Tsyzer, [1993]. “Test Responses Compaction in Accumulators with Rotate Carry Adders,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 4, pp. 531-539, Apr.
[14]. Krishnendu Chakrabarty and John P. Hayes, [1997]. “On the Quality of Accumulator-Based Compaction of Test Responses,” IEEE Trans. On Computer-Aided Design Of Integrated Circuits And Systems, Vol. 16, No. 8, Aug.
[15]. X. Sun and M. Serra, [1993]. “Design and Implementation of a Merged On-Line and Off-Line Self Testable Architecture,” Proc. IEEE Int'l Workshop Defect and Fault Tolerance in VLSI Systems, pp. 247-254, Oct.
[16]. M. Chatterjee and D.K. Pradhan, [2003]. “A BIST Pattern Generator Design for Near-Perfect Fault Coverage,” IEEE Trans. Computers, Vol. 52, No. 12, Dec.
[17]. C. Fagot, O. Gascuel, P. Girard, and C. Landrault, [2003]. “A Ring Architecture Strategy for BIST Test Pattern Generation,” J. Electronic Testing: Theor y and Applications, Vol. 19, pp. 223-231.
[18]. M. Abramovici, C.E. Stroud, and J.M. Emmert, [2004]. “Online BIST and BIST-Based Diagnosis of FPGA Logic Blocks,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 12, pp. 1284-1294, Dec.
[19]. A. Steininger and J. Vilanek, [2002]. “Using Offline and Online BIST to Improve System Dependability—The TTPC-C Example,” Proc. IEEE Int'l Conf. Computer Design: VLSI in Computers and Processors, pp. 277-280.
[20]. H. Al-Asaad, B.T. Murray, and J.P. Hayes, [1998]. “Online BIST for Embedded Systems,” IEEE Design and Test of Computers, Vol. 15, No. 4, pp. 17-24, Oct.-Dec.
[21]. C. Scherrer and A. Steininger, [1999]. “On the Necessity of On-Line-BIST in Safety-Critical Applications—A Case Study,” Proc. 29th Ann. Int'l Symp. Fault-Tolerant Computing, p. 208.
[22]. H. Al-Asaad, J.P. Hayes, and B.T. Murray, [1996]. “Design of Scalable Hardware Test Generators for On-Line BIST,” Proc. IEEE Int'l On-Line Testing Workshop, pp. 164- 167.
[23]. M. Abramovici, C. Stroud, B. Skaggs, and J. Emmert, [2000]. “Improving On-Line BIST-Based Diagnosis for Roving STARs,” Proc. Sixth IEEE Int'l On-Line Testing Workshop, pp. 31.
[24]. M. Pflanz, K. Walther, C. Galke, and H.T. Vierhaus, [2003]. “On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check,” J. Electronic Testing: Theory and Applications, Vol. 19, pp. 501-510.
[25]. M. Nicolaidis and Y. Zorian, [1998]. “On-Line Testing for VLSI-A Compendium of Approaches,” J. Electronic Testing: Theory and Applications, Vol. 12, Nos. 1-2, pp. 7-12.
If you have access to this article please login to view the article or kindly login to purchase the article

Purchase Instant Access

Single Article

North Americas,UK,
Middle East,Europe
India Rest of world
USD EUR INR USD-ROW
Pdf 35 35 200 20
Online 35 35 200 15
Pdf & Online 35 35 400 25

Options for accessing this content:
  • If you would like institutional access to this content, please recommend the title to your librarian.
    Library Recommendation Form
  • If you already have i-manager's user account: Login above and proceed to purchase the article.
  • New Users: Please register, then proceed to purchase the article.