Software Model to Create Data Profile for Analysis of Gray Bus Codec

Kamal K Mehta*, Sushil Dubey**, Sharma H.R***
* Associate Professor, Department of Computer Science & Engineering, SSCET, Bhilai.
** MCA, III Semester. Student, SSCET, Bhilai.
*** Director, Chatrapati Shivaji Institute of Technology, Durg (C.G.).
Periodicity:October - December'2010
DOI : https://doi.org/10.26634/jse.5.2.1337

Abstract

Low power design has gain attention of designers, since a decade. Various methods have been proposed in literature. One way is to adopt Bus Encoding scheme. It has been further observed that, efficiency proof of proposed bus encoding method does not have concrete base.  Task becomes complex when we talk about implementation on computer system. In this paper, a modeling technique for Bus CODEC is presented. Model is made versatile to use for any type of bus encoding technique. Major focus was towards dynamic power dissipation, which in turn depends on operating frequency, drain to drain supply voltage, capacitance and switching activity. Work has been done to find out optimum value of supply voltage. Strong attempt has been witnessed for dynamic changing frequency. None of the effort has been seen in turns of data profiling. This paper presents a software model to maintain record of data flow across computer channel. A processor of MHz. frequency has been taken into consideration. Database has been created to support variety of CPU available. Developed system enables to set input as per desired sequence. Subsequently transition activity has been calculated. Care has been taken to make model versatile, that we can use it for variety of Bus Encoder/Decoder. The only restriction is, it should not contain memory elements. This paper includes extensive experimental work of Gray Bus Encoding scheme. System is having capability to update database gradually, as we go on implementing our task. Work has been further extended to maintain library having multiple CPU, with different manufacturing scale, supply voltage and operational frequency.  Result has been compiled taking random dataset into consideration.

Keywords

CMOS Transition activity,Gray Bus Encoding,Low power micro electronics, Dynamic power dissipation,VLSI,Software Simulation.

How to Cite this Article?

Kamal K Mehta, Sushil Dubey and Sharma H.R (2010). Software Model to Create Data Profile for Analysis of Gray Bus Code C. i-manager’s Journal on Software Engineering, 5(2), 58-62. https://doi.org/10.26634/jse.5.2.1337

References

[1]. Padmanabhan Balasubramanian, C. Hari Narayan, and Karthik Anantha “Low power design of digital combinational circuits with complementary CMOS Logic”, International Journal of Electronics and Systems Vol. 1 No. 1.
[2]. T. Kuroda, (2002). “Low power high speed CMOS VLSI design,” Proc. of IEEE International Conf. on Computer Design, pp. 310-315.
[3]. Farid N. Najm, (1994). “A Survey of Power Estimation Technique in VLSI Circuits” IEEE transaction on VLSI, Dec pp. 1-19.
[4]. Technical disclosure presents new options for chip scaling “Texas Instruments Researchers Outline path to reduce chip power consumption, increase performance” physics.com science:physics:tech: nano:news.
[5]. Brain Carlson, Bill Giolma, (2008). “ SmartReflextm Power and Performance Management Technologies: reduced power consumption, optimized performance” white paper by Texas Instruments February .
[6]. Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru “Estimation of propagation Delay considering Short- Circuit Current for Static CMOS Gates” IEEE Transactions on Circuits and Systems.
[7]. Derek Curd, (2007). “Power Consumption in 65 nm FPGAs” Xilink White Paper 246(V1.2) Virtex-5 FPGAs February 1, 2007.
[8]. K. Eshraghian and N.H.E. Weste, (1993). “ Principal of CMOS VLSI Design”, Addision Wesley, United States of America .
[9]. S. Osborne, A.T. Erdogan, T. Arslan, and D. Robinson, (2002). “Bus Encoding architecture for low power implementation of an AMBA-based SoC platform.” IEE Proc. Computer digital Tech. Vol. 149, No. 4 July.
[10]. Quick Logic corporation, (2004). “Low Power design technique” Application note 80.
[11]. Samta Gajbhiye, Mehta K.K., H.R. Sharma, (2007). “Unidistance Encoding scheme for reduction of Bus Transition Activity” i-manager’s Journal on Software Engineering, April-June, Vol. 1 No.4, pp 70-74, ISSN-0973- 5151.
[12]. Mehta K.K., H.R. Sharma, (2008). “Evaluation of Unidistance CODEC for 4 to 32 bit information for power Reduction Initiatives” i-manager’s Journal on Software Engineering, Jan-Mar, Vol. 2 No.3 pp. 57-60, ISSN-0973- 5151.
[13]. Frank Poppen, (2001). “Low Power Design Guide”, Version 30.06.00 A technical report given around 2001.
[14]. J. Yang, and R. Gupta, (2001). “FV Encoding for Low power Data I/O”, ACM/IEEE Int. Symposium on Low power Electronic Design, pp. 84-87.
[15]. M.R. Stan, and W.P. Burleson, (1995). “Bus invert coding for low power I/O” IEEE Transaction on very Large Scale Integration (VLSI) systems, pp. 49-58,Vol. 3.
[16]. S. Osborne, A.T. Erdogan, T. Arslan, and D. Robinson, (2002). “Bus Encoding architecture for Low power implementation of an AMBA-based SoC Platform” IEEE 2002 Proc. Computer Digit Tech, Vol. 149,No.4 July .
[17]. Sotiriadis, P.P. (2002). “Interconnect modeling & optimization in deep sub-micron technology”, Thesis (Massachusetts Institute of Technology), May.
If you have access to this article please login to view the article or kindly login to purchase the article

Purchase Instant Access

Single Article

North Americas,UK,
Middle East,Europe
India Rest of world
USD EUR INR USD-ROW
Online 15 15

Options for accessing this content:
  • If you would like institutional access to this content, please recommend the title to your librarian.
    Library Recommendation Form
  • If you already have i-manager's user account: Login above and proceed to purchase the article.
  • New Users: Please register, then proceed to purchase the article.