Low power design has gain attention of designers, since a decade. Various methods have been proposed in literature. One way is to adopt Bus Encoding scheme. It has been further observed that, efficiency proof of proposed bus encoding method does not have concrete base. Task becomes complex when we talk about implementation on computer system. In this paper, a modeling technique for Bus CODEC is presented. Model is made versatile to use for any type of bus encoding technique. Major focus was towards dynamic power dissipation, which in turn depends on operating frequency, drain to drain supply voltage, capacitance and switching activity. Work has been done to find out optimum value of supply voltage. Strong attempt has been witnessed for dynamic changing frequency. None of the effort has been seen in turns of data profiling. This paper presents a software model to maintain record of data flow across computer channel. A processor of MHz. frequency has been taken into consideration. Database has been created to support variety of CPU available. Developed system enables to set input as per desired sequence. Subsequently transition activity has been calculated. Care has been taken to make model versatile, that we can use it for variety of Bus Encoder/Decoder. The only restriction is, it should not contain memory elements. This paper includes extensive experimental work of Gray Bus Encoding scheme. System is having capability to update database gradually, as we go on implementing our task. Work has been further extended to maintain library having multiple CPU, with different manufacturing scale, supply voltage and operational frequency. Result has been compiled taking random dataset into consideration.