References
[1]. Padmanabhan Balasubramanian. C.Hari Narayan,
and Karthik Anantha “Low power design of digital
combinational circuits with complementary CMOS
Logic”. International Journal of Electronics and Systems,
Vol 1, No 1.
[2]. T. Kuroda, (2002). “Low power high speed CMOS VLSI
design,” Proc. of IEEE International Conf. on Computer
Design, pp 310-315.
[3]. Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru.
“Estimation of propagation Delay considering Short-
Circuit Curent for Static CMOS Gates” IEEE Transactions on
Circuits and Systems.
[4]. Farid N. Najm, (1994). ”A Survey of Power Estimation
Technique in VLSI Circuits” IEEE transaction on VLSI, Dec pp
1-19.
[5]. K.Eshraghian and N.H.E.Weste, (1993). “Principal of
CMOS VLSI Design”, Addision Wesley, United States of
America.
[6]. S.Osborne, A.T. Erdogan, T.Arslan, and D. Robinson,
(2002). “Bus Encoding architecture for low power
implementation of an AMBA-based SoC platform.” IEE
Proc. Computer digital Tech. Vol 149, No. 4 July.
[7]. Quick Logic corporation (2004). “Low Power design
technique” Application note 80.
[8]. Frank Poppen (2001). “Low Power Design Guide”,
Version 30.06.00 A technical report given around.
[9]. J. Yang and R. Gupta, (2001). “FV Encoding for Low
power Data I/O”,ACM/IEEE Int. Symposium on Low power
Electronic Design, pp 84-87.
[10]. M.R. Stan and W.P. Burleson, (1995). “Bus invert
coding for low power I/O”, IEEE Transaction on very Large
Scale Integration (VLSI) systems, pp 49-58, Vol.3.
[11]. Technical disclosure presents new options for chip
scaling ”Texas Instruments Researchers Outline path to
reduce chip power consumption ,increase performance” physics.comscience:physics:
tech:nano:news.
[12]. Brain Carlson, bill Giolma (2008). “SmartReflex TM
Power and Performance Management Technologies:
reduced power consumption, optimized performance”
white paper by Texas Instruments february.
[13]. S. Osborne, A.T. Erdogan, T. Arslan and D.Robinson
(2002). ”Bus Enoding architecture for Low power
implementation of an AMBA-based SoC Platform” IEE
Proc. Computer Digit Tech Vol.149, No.4 July.
[14]. Mehta K K, Dr. H.R. Sharma (2007). “Unidistance
Encoding scheme for reduction of Bus Transition Activity”,
i-manager’s Journal on Software Engineering, April-June
Vol. 1, No.4 pp 79-83.
[15]. Mehta K K, Dr. H.R. Sharma (2008). “Evaluation of
Unidistance CODEC for 4 to 32 bit information for Power
Reduction Initiatives” i-manager’s Journal on Software
Engineering,Jan-March, Vol.2, No. 3. pp 57-60.
[16]. Sotiriadis, P.P. (2002). “Interconnect modeling &
optimization in deep sub-micron technology”, Thesis
(Massachusetts Institute of Technology), May.
