References
[1]. T. Yuan, D. A. Buchanan, C. Wei, D. J. Frank, K. E.
Ismail, L. Shih-Hsien, G. A. Sai-Halasz, R. G. Viswanathan,
H. J. C. Wann, S. J. Wind, and W. Hon-Sum, (1997). "CMOS
scaling into the nanometer regime", Proceedings of the
IEEE, Vol. 85, No. 4, pp. 486-504.
[2]. Kaushik Roy and Sharat C. Prasad, (2009). “Low
Power CMOS VLSI Circuit Design”, Wiley India Pvt. Ltd, New
Delhi.
[3]. Gary Yeap, (2009). “Practical Low Power Digital VLSI
Design”, Springer International Edition, New Delhi.
[4]. P. Gelsinger, (2004). “Gigascale Integration for
Teraops Performance - Challenges, Opportunities, and New Frontiers,” in Proceedings of the 41st Design
Automation Conference, p. xxv.
[5] Fred Pollack, (1999). “IEEE – 32nd Annual International
Symposium on Microarchitecture”, Haifa, Israel, 16-18
Nov. www.huron.cs.ucdavis.edu/Micro32/homepage.
html.
[6] B. J. Sheu et al., (1987). “BSIM Berkeley short-channel
IGFET model for MOS transistors,” IEEE J. Solid-State
Circuits, Vol. SC-22, pp. 558–566, Aug.
[7]. Sung Mo Kang and Yusuf Leblebici, (2003). “CMOS
Digital Integrated Circuits-Analysis and Design”, Tata Mc
Graw Hill, Third Edition, New Delhi.
[8]. Microwind and Dsch version 3.1 software manual.