In Very Deep-submicron (VDSM) systems, the scaling of ULSI ICs has increased the sensitivity of CMOS technology to cause various noise mechanisms such as power supply noise, crosstalk noise, leakage noise, etc. In VDSM technology distance between the data bus lines is reduced, so coupling capacitance is dominating factor. The coupling capacitance (CC) is between long parallel wires. The load capacitance (CL) defines the wire-to-substrate capacitance. Unfortunately, in VDSM systems, the coupling capacitance is of magnitude several times larger than the loading capacitance. The coupling capacitance causes logical malfunction, delay faults, and power consumption on long on-chip data buses. An important effect of the coupling capacitance is Cross talk. Crosstalk is mainly dependent on several factors: drive strength, wire length/spacing, edge rate and propagation duration.

The crosstalk noise produces from the coupling capacitance. Such faults may affect data on data bus. The severity of this problem depends on fault duration. To avoid this condition and to guarantee signal integrity on the on-chip communication, a fault tolerant bus can be adopted. This could be achieved by implementing error-correcting codes (ECCs), providing on-line correction and do not require data retransmission.

The 8-bit data bus is implemented in 1200nm, 180nm, 120nm, 90nm and 65nm technologies and simulation results shows that crosstalk increases as the technology scales down. For reliable transmission of the data ECC techniques is placed on the data bus. We employed a Hamming code as ECC for 8-bit fault tolerant data bus. This is implemented in 1200nm, 180nm, 120nm, 90nm and 65nm technology. The simulation results show that the average Power varies from 48.054mW to 0.235m, and Maximum delay varies from 3.437ns to 0.092ns respectively.