Advances in silicon technology have made possible the design of very large scale integration (VLSI) chips. The size of these designs has reached a level where the design activity is carried out by a team of designers rather than an individual. The complexity of the designs and the merging of functional islands from different designers can lead to mistakes (bugs) in the chip.

This paper details the methods used by the Subsystems Electronics hardware design group (based at IBM Havant) to minimise the possibility of releasing a chip containing bugs.  In most cases the design will have cost and schedule constraints, and there is a trade-off between the amount of time and exhibit expended at the design and simulation phases, and the risk of sending a chip for fabrication before all the bugs have been found. The problem of determining when a chip should be released for fabrication has been addressed by the use of statistical analysis to assess when the simulation is complete or no longer likely to find mistakes.