References
[1]. International Technology Roadmap for Semiconductors,
(SIA). Retrieved from http://itrs2.net, 2016 edition of ITRS.
[2]. K.G. Cheng, and A. Khakifirooz, (2016). “Fully
depleted SOI (FDSOI) technology”. Sci. China Inf. Sci.,
Vol.59, pp.1-15.
[3]. H.C. Poon, L.D. Yau, R.L. Johnston, and D. Beecham, (1974). “DC model for short-channel IGFET’s”. In: IEDM
Tech. Dig., pp.156–159.
[4]. M.J. Kumar, and A. Chaudhry, (2004). “Controlling
Short Channel Effects in Deep-Submicron SOI MOSFETs for
Improved Reliability: A Review”. IEEE Trans. Device and
Materials Reliability, Vol.4, No.1, pp.99-109.
[5]. J.J. Sanchez, K.K. Hsueh, and T.A. DeMassa, (1989).
“Drain-engineered hot electron-resistant devices
structures: A review”. IEEE Trans. Electron Devices, Vol.36,
No.6, pp.1125–1132.
[6]. S.D. Kim, C.M. Park, and J.C.S. Woo, (2002).
“Advanced source/drain engineering for box-shaped
ultrashallow junction formation using laser annealing and
pre-amorphization implantation in sub-100-nm SOI
CMOS”. IEEE Trans. Electron. Devices, Vol.49, No.10,
pp.1748–1754.
[7]. A. Kranti, and G. Alastair Armstrong, (2006).
“Optimization of the source/drain extension region profile
for suppression of short channel effects in sub-50 nm DG
MOSFETs with high-k gate dielectrics”. Semicond. Sci.
Technol., Vol.21, No.12, pp.1563–1572.
[8]. W. Long, H. Ou, J.M. Kuo, and K. K. Chin, (1999). “Dual
Material Gate (DMG) field effect transistor”. IEEE Trans.
Electron. Devices, Vol.46, No.5, pp.865–870.
[9]. M.J. Kumar, and A. Chaudhry, (2004). “Twodimensional
analytical modeling of fully depleted Dual-
Material Gate (DMG) SOI MOSFET and evidence for
diminished short-channel effects”. IEEE Trans. Electron Devices, Vol.51, No.4, pp.569–574.
[10]. V.K. Mishra, and R.K. Chauhan, (2017).
“Performance analysis of modified source and TDBC
based fully-depleted SOI MOSFET for low power digital
applications”. Journal of Nanoelectronics and
Optoelectronics, American Scientific Publisher, Vol.12,
No.1, pp.59-66.
[11]. X. Zhou, (2000). “Exploring the novel characterstics
of Hetro-Material gate field effect transistors (HMGFETs)
with gate material engineering”. IEEE Trans. Electron
Devices, Vol. 47, No.1, pp.113-120.
[12]. V.K. Mishra, and R.K. Chauhan, (2017). “Performance
Analysis of Fully Depleted SOI Tapered Body Reduced
Source (FD-SOI TBRS) MOSFET for Low Power Digital
Applications”. Advances in Intelligent Systems and Soft
Computing, Springer AISC Series, Vol.516, pp.361-368.
[13]. V.K. Mishra, and R.K. Chauhan, (2016).
“Performance Analysis of Fully Depleted Ultra Thin-Body
(FD UTB) SOI MOSFET based CMOS Inverter Circuit for Low
Power Digital Applications”. Advances in Intelligent
Systems and Soft Computing, Springer AISC Series,
Vol.434, pp.375-382 .
[14]. V.K. Mishra, and R.K. Chauhan, (2016). “Area Efficient Layout Design of CMOS Device for Digital Circuit Applications”. Journal of Nanoengineering and
Nanomanufacturing, American Scientific Publisher, Vol.6,
No.3, pp.188-192.