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Delay Calculation Of Gray Bus Encoder As Per Microelectronic Standard

Kamal K Mehta*, Aakanksha S.Choubey M**, M. Kowar***, Sharma H.R****

* Associate Professor, Department of Computer Science &Engineering, SSCET, Bhilai.

** Lecturer, Department of Computer Science &Engineering, SSCET, Bhilai.

*** Principal, Bhilai Institute of Technology, Durg (C.G).

**** Principal, Chatrapati Shiwagi Institute of Technology, Durg (C.G).

Periodicity:October - December'2009
DOI : https://doi.org/10.26634/jee.3.2.1049

Abstract

CMOS based system using complementary logic has dominated other design concept, mainly because of simple fabrication process, low power requirements and good voltage swing response. In modern computing system it requires to have a feature of low power consumption without scarifying the speed. In such case the power requirement is mainly influenced by transition activity at the output node. Literature survey shows that lot of technique has been proposed for static component of power budget, but dynamic component is still to be considered. Encoding methods have been proposed to reduce transition activity. Scheme used to reduce dynamic power is called as Bus Encoding Technique. Mathematical model have been proposed to get efficiency factors along with probabilistic model and expectation based analysis. Based upon features of bus encoding scheme, specific application has been proposed. Gray encoding scheme is recommended for generalized application. Many factors were used to find out efficiency of encoding method. Power requirement and delay are proven to be inversely proportional to each other. To recommend any system, it requires having positive result in terms of overhead. This paper aims to target Grey Encoding scheme for calculating Delay. Work has been extended to consider 0.25-micro meter manufacturing technology. Overhead has been calculated in terms of delay. It has resulted as 661.320075 pico seconds. This is tolerable as compared to integration rate of VLSI system.

Keywords

Transition Activity, Gray Bus Encoding, Low Power Micro Electronics, CMOS, Dynamic Power Dissipation, VLSI.

How to Cite this Article?

Kamal Mehta, Aakanksha S. Choubey, M. Kowar and H. R. Sharma (2009). Delay Calculation of Gray Bus Encoder as per Microelectronic Standard. i-manager’s Journal on Electrical Engineering, 3(2), Oct-Dec 2009, Print ISSN 0973-8835, E-ISSN 2230-7176, pp. 59-64. https://doi.org/10.26634/jee.3.2.1049

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Delay Calculation Of Gray Bus Encoder As Per Microelectronic Standard

Abstract

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References

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