Analysis of Modular Multipliers

Tallaka Yamini*, A. B. Yadav**, K. Neelima***
* PG Scholar, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupati, India.
** Associate Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupati, India.
*** Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, Tirupati, India.
Periodicity:June - August'2016


This paper proposes a simple and efficient Modular Multiplication algorithm. Montgomery modular multipliers can be implemented accordingly. Based on the Montgomery technique, both SCS and FCS are used by the Carry save format and also the modified SCA. The proposed SCS have used CCSA. To increase the performance of the cryptosystem, the modular multiplication is interleaved by serial and parallel radix-4 modular multipliers and also the same for normal multiplication. By comparing this technique, critical path and clock cycles are reduced. Now these techniques are used in Verilog HDL Virtex-3E using Xilinx ISE 14.5 design suite.


Carry-Save Addition, Montgomery Multiplication, Interleaved Multiplication, Public-Key Cryptosystems.

How to Cite this Article?

Yamini,T., Yadav, A.B., and Neelima, K. (2016). Analysis of Modular Multipliers. i-manager's Journal on Electronics Engineering, 6(4), 24-30.


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