Multiplication plays an important role in most mathematical applications. Among the four arithmetic operations, multiplier is the most important one. In this paper, the authors have proposed a multiplier which operates on two 24 bit of digital numbers, which is a 24 bit multiplier. In order to construct a 24 bit multiplier, the authors used Dadda reduction technique. Dadda reduction technique operates on two 24 bit numbers , hence called a 24 bit multiplier. These higher bit multipliers are used in floating point multiplications, i.e., floating point operates based on single precision and double precision numbers. In order to operate them while doing multiplication, the mantissa has 24 bits, whereas double precision requires 48 bits. This is designed using Verilog Hardware description language. This is simulated using Xilinix ISE 10.1 and being implemented on Spartran 3E of FPGA.