i-manager Publications

I/O Average And Maximum CurrentConsumption Calculation

Andrey Malkov*, Lin Wang**, Evgeny Shevchenko***

* I/O Design Group, Freescale Semiconductor, Moscow, Russia.

** Hardware Application Team, Freescale Semiconductor, Shanghai, China.

*** Manager, I/O Design Team, Freescale Semiconductor, Moscow, Russia.

Periodicity:June - August'2014
DOI : https://doi.org/10.26634/jele.4.4.3194

Abstract

Power Integrity (PI) is becoming increasingly important in today's high-speed digital I/O interfaces. Power integrity for I/O interfaces is related to the voltage variations in the power/ground network due to the noise. The power/ground noise causes various problems in high-speed systems, such as logic failure, EMI, timing delay, and jitter. For the Power Integrity analysis of the I/O padring of the chip, it is very important to quickly calculate I/O current consumption at the early stage of the project, without running extensive time-consuming spice simulations of entire I/O bank. PI analysis needs both I/O padring and PCBdata, and simulation tool considers them simultaneously [5],[6],[7],[10]. Two useful formulas are given in this article and explained below that can easily allow to estimate average and maximum IO current consumption, using example of i.MX6 series applications processors of Freescale Semiconductor, Inc. Resulting numbers correlate well with real I/O circuit spice simulation data.

Keywords

I/O Design, Power Integrity, Current Consumption, Average Current, Maximum Current.

How to Cite this Article?

Malkov, A., Wang, L., and Shevchenko, E. (2014). I/O Average And Maximum Current Consumption Calculation. i-manager’s Journal on Electronics Engineering, 4(4), 1-4. https://doi.org/10.26634/jele.4.4.3194

References

[1]. Henry W. Ott, (2009). “Electromagnetic Compatibility Engineering”, ISBN 978-0-470-18930-6pp. 428.

[2]. Lee W. Ritchey, “Right The First Time - A Practical Handbook on High-Speed PCB and System Design”, pp. 353.

[3]. Freescale Semiconductor i.MX6 series applications processors Datasheet at http://www.freescale.com/ webapp/sps/site/prod_summary.jsp?code=i.MX6Q&fps p=1&tab=Documentation_Tab

[4]. Vishram S. Pandit, Woong Hwan Ryu, Myoung Joon Choi, “Power Integrity for I/O Interfaces: With Signal Integrity/ Power Integrity Co-Design (Prentice Hall Signal Integrity Library)”, ISSBN -13: 970-0-137-01119-3, pp. 1- 383.

[5]. M. Swaminathan, E. Engin, “Power Integrity Modeling and Design for Semiconductors and Systems”, Prentice Hall, press.

[6]. M.J. Choi, and V. Pandit, (2009). “SI/PI Co-Analysis for I/O Interfaces,” IBIS Summit.

[7]. Eric Bogatin, (2009). “Signal and Power Integrity – Simplified2nd Edition”, Hardback.

[8]. Masanori Hashimoto & Raj Nair, (2011). “Power Integrity for Nanoscale Integrated Systems”, A practical handbook for designing with power supply noise.

[9]. Vishram S. Pandit and others, (2009). “SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity”, DESIGNCON.

[10]. I. Novak (2008). (Executive Editor), “Power Distribution Design Methodologies” IEC, ISBN: 978-1-931695-65-7.

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I/O Average And Maximum CurrentConsumption Calculation

Abstract

Keywords

How to Cite this Article?

References

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