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Design and Implementation of Wallace Tree Multiplier and Its Applications in FIR Filter

R. Archana*, A. Nallathambi**

*-** Electronics and Communication Engineering, Roever Engineering College, Perambalur, Tamilnadu, India.

Periodicity:January - June'2024

Abstract

Limited Drive Reaction channels are the most significant component in signal handling and correspondence. The architecture of a FIR filter includes a delay unit, multiplier, and adder. Along these lines, execution of FIR channel is chiefly founded on multiplier. This paper presents FIR filter execution of the Wallace multiplier. Delay, power, and area performance can all be improved with this method. VHDL is used to write the code, which is simulated using ModelSim 6.3c and synthesized using Xilinx ISE 9.2i. The design is then implemented in the Spartan-3 FPGA.

Keywords

Finite Impulse Response (FIR), Wallace Tree Multiplier (WTM), Logic gates, Arithmetic Logic Units (ALU), Digital Circuit Design, Performance Optimization.

How to Cite this Article?

Archana, R., and Nallathambi, A. (2024). Design and Implementation of Wallace Tree Multiplier and Its Applications in FIR Filter. i-manager’s Journal on Circuits and Systems, 12(1), 36-43.

References

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