In this paper, the authors present a simulation study in order to carry out static and dynamic analysis of CNTFET-based digital circuits, in the semi-empirical compact model for CNTFETs, which was already proposed with, both the quantum capacitance effects and the sub-threshold currents. To verify the validity of the obtained results, they are compared with those of the Stanford-Source Virtual Carbon Nanotube Field-Effect Transistor (VS-CNFET) model. This comparison is made through some simulations of digital circuits. In particular they have considered XOR gate, but emphasizing that the proposed procedure can be applied to any logic gate based on CNTFET. As regards the static conditions, the two models behave in a manner virtually identical, while, as regards the dynamic analysis, there is a remarkable differences between two models in terms of propagation delays and rise and fall times.