Memory is one of the key elements in any of the electronic systems. But, Multiple Cell Upsets (MCU's) are becoming serious reliability problems to the memories when they are operated in radiation environment. So to protect memories, complex Error Correcting Codes (ECC) are proposed to overcome data corruption but the issue with them is that they need higher delay overheads., Decimal Matrix Code (DMC) has been proposed for the protection of memories which uses a decimal algorithm to enhance memory reliability. In DMC, the area of the circuit is minimized by using Encoder Reuse Technique (ERT) (i.e. encoder is reused in the decoder). But it requires a higher number of redundancy bits. So, to reduce redundancy bits and to improve error correcting capability, another technique called Parity Matrix Code (PMC) is used with the same algorithm as that of DMC with reduced redundancy bits and performance overheads. The drawback of existing DMC algorithm is that it requires more number of redundancy bits. This drawback was rectified in the modified PMC technique thus reducing the number of redundancy bits used for detecting and correcting the data. Thus modified PMC technique is more advantageous than an existing DMC technique because it has less number of redundancy bits with maximum error correction capability and Efficient Power, Performance and Area (PPA).