Design and implementation of memory devices are becoming a challenge for the memory designers due to various limitations. Leakage power dissipation and low data stability are the main constraints, while designing memory integrated circuits. In this paper, a new 8T Static Random Access Memory (SRAM) cell, that adopts a single bit line scheme has been proposed to limit the leakage current as well as to gain high data stability. The proposed circuit consumes 671.22 pA leakage current during idle state of the circuit. It shows the high data stability 343 MV and 329 MV during read and hold state, respectively. Additionally, this paper contains 64-bit memory unit of the proposed 8T SRAM cell (8 x 8) array. The array comprises of row decoder, column decoder, and sense amplifier. The proposed 8T SRAM cell is 16.45X and 43.78X fast during read 0 and read 1 operations, respectively, while during write 0 and write 1 operations the delay is reduced up to 8.05% and 8.46%, respectively when compared with (8 x 8) array of 6T SRAM cell. During read 0 and read 1, it is fast by 16.45X and 43.78X, respectively. The average power consumption during read 1/0 and write 1/0 operations are 99.5% /60.05% and 99.61% /59.82% less as compare to 6T SRAM array, respectively.