A novel Diode Free Adiabatic Logic (DFAL) based Threshold Inverter Quantizer (TIQ) is suggested in this work for
implementing a 3-bit Flash type Analog to Digital Converter (FADC). For appropriate implementation of such TIQ, there is
a necessity of rehabilitated reference voltage for each of the comparator and this task is accomplished methodically by
sizing the transistors of the TIQ comparators. The suggested work is carried out with TSMC 65 nm Technology on Cadence-
Virtuoso-IC616 version. The average power dissipation by the proposed FADC simulated at 1.2 V and and for 1fF capacitive
load is 5.5 μW, which is 66 % less than that of the power consumed by CMOS-TIQ based FADC at 100 Hz.