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Method of 2.5 V RGMII Interface I/O Duty Cycle and Delay Skew Enhancement

Sergey Kuznetsov*, Andrey Malkov**, Evgeny Shevchenko***, Sergey Somov****

Ph.D Student of Moscow Institute of Electronic Technology (MIET), Intern of I/O Library Design Team, NXP Semiconductors Moscow, Russia

Chief I/O Design Architect of NXP Semiconductors Moscow, Russia

Ph.D of Engineering Sciences, I/O Library Design Team Manager of NXP Semiconductors Moscow, Russia

Design Enablement NXP Semiconductors Moscow Site Manager, Russia

Periodicity:December - February'2018
DOI : https://doi.org/10.26634/jele.8.2.14133

Abstract

In this paper, the problem of reducing difference between rise and fall delays (output delay skew) of Input/Outpuut (I/O) cells and duty cycle enhancement to meet 2.5 V Reduced Gigabit Media Independent Interface (RGMII) 2.0 interface I/Os timing requirements at Gigabit Ethernet 125 MHz clock speed was investigated and analyzed. Stacked I/O design specifics (reference voltages and their instability) were considered for example design of 2.5 V I/Os in 28 nm technology with 1.8V dual-gate-oxide (dgo) transistors (Yoshida, 2017). Testbench for test I/O bank Layout Parasitic Extraction (LPE) netlist spice simulations was created in Cadence Virtuoso design environment for I/O rise/fall delays and duty cycle evaluation at bank-level including package Resistor-Inductor-Capacitor (R-L-C) and T-line models, and worst data toggle patterns were used to take simultaneously switching effects into account. Method for connecting decoupling capacitors to reference voltages was used to achieve reduced voltage noise, adjusted rise/fall delays, reduced skew, and output signal stabilized for both single I/O and I/O bank. Analysis was carried out for various values of decoupling capacitors to calculate appropriate one and meet the given RGMII specification timing requirements.

Keywords

Reduced Gigabit Media Independent Interface (RGMII) Interface, Gigabit Ethernet, Stacked Input/Output Cell, I/O Bank, Simultaneously Switching Output (SSO), Decoupling Capacitors, Timing, Duty Cycle, Rise/Fall Delay Skew, Data Toggle Pattern, Cadence.

How to Cite this Article?

Kuznetsov. S., Malkov. A., Shevchenko. E and Somov. S (2018). Method of 2.5 V Rgmii Interface I/O Duty Cycle and Delay Skew Enhancement. i-manager's Journal on Electronics Engineering, 8(2), 1-5. https://doi.org/10.26634/jele.8.2.14133

References

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