Performance Metrics and Temperature Variability in a 16 nm Spacer FinFET

Sangeetha Mangesh*, Krishan K. Saini**, P. K. Chopra***
* Assistant Professor, Department of Electronics & Communication Engineering, JSS Academy of Technical Education, Noida, Uttar Pradesh .India
** Chief Scientist, National Physical Laboratory, New Delhi, India .
*** Professor and Head, Department of ECE & EI, Ajay Kumar Garg Engineering College, Ghaziabad, Uttar Pradesh, India.
Periodicity:June - August'2018


Driven by Moore's law, the scaling of devices has reached nanoscale. The journey of miniaturizations has encountered several challenges to attain desired electrical characteristics to meet the demand in the era of information technology. A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device, being a major building block for designing both analog and digital circuits in IC design technology, has consequently undergone multiple structural variations to meet these challenges.

Planar as well as SOI multi-gate MOSFET devices are the front runners, amongst them. These devices have better controlling ability due to inherent advantage of multi-gate technology. This paper, carries out an analysis of an improved Fin Field Effect Transistor (FinFET) device designed for 16 nm channel length. Its performance metrics are compared with a regular design. A 16 nm FinFET design using nitride layers is implemented using Technology Computer Aided Design (TCAD) and analysis of threshold voltage, transconductance, Subthreshold Slope (SS), leakage current, charge density variations along fin, quasi Fermi Energy variations of electrons, electron net electron charge, carrier recombination, and mobility along the channel and an ability to withstand temperature is carried out. Timing analysis is also carried out implementing a resistive load inverter employing both the devices. The results are analyzed and compared with simple planar counterpart along with justification claiming the improved spacer FINFET design along with its limitations.


ITRS- International Technology Roadmap for Semiconductors, SOI (Silicon on Insulator), DIBL (Drain Induced Barrier Lowering), GIDL (Gate Induced Leakage Current), SS (Subthreshold Slope).

How to Cite this Article?

Mangesh. S., Saini. K. K and Chopra. P. K (2018). Performance Metrics and Temperature Variability in a 16 nm Spacer FinFET. i-manager's Journal on Electronics Engineering, 8(4), 41-49.


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