A Design and Implementation of High Speed Ieee-754 Double Precision Floating Point Unit Based on Vedic Techniques

Rahul Kumar Agrawal*, Rhythm Tyagi**, Madan Mohan Tripathi***
DOI : https://doi.org/10.26634/jele.8.1.13836

Abstract

In this paper, a high speed 64-bit double precision Floating Point Unit (FPU) using Vedic mathematics is proposed. In a general processor, the multiplication and division architectures play a crucial role in deciding the overall speed of the system. However, the standard algorithms are sequential units and reduce the performance of the processor. Vedic Mathematics on the other hand offers a new holistic approach of realizing these operations in a combinational unit. In the proposed architecture, the multiplication operation has been implemented using a 54-bit Vedic multiplier based on Urdhva Tiryagbhyam Algorithm while an optimized binary division architecture using Nikhilam Sutra is realized. The proposed method is coded in Verilog High Description Language (HDL), synthesized for Spartan 6 Field-Programmable Gate Array (FPGA) board and simulated using Xilinx Vivado Design Suite. An operating frequency of 205.08 MHz has been attained, which is 92.61% faster than the conventional implementation of a 64-bit floating point unit. The number of slice registers required for the overall realization of the FPU has also been reduced significantly by 94.3% and hence reducing the area requirement of the FPU in a general processor.

Keywords

Floating Point Unit, Vedic Mathematics, Verilog, Double Precision, FPGA.

How to Cite this Article?

Agrawal, R.K., Tyagi, R., Tripathi, M.M. (2017). A Design and Implementation of High Speed Ieee-754 Double Precision Floating Point Unit Based on Vedic Techniques. i-manager’s Journal on Electronics Engineering, 8(1), 19-27. https://doi.org/10.26634/jele.8.1.13836

References

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