Power Dissipation and Switching Speed Analysis of a CMOS Full adder in Deep Submicron and Nanoscale Technologies

Manish Kumar*, **
* Assistant Professor, Department of Electronics and Communication Engineering, NERIST (Deemed University), Arunachal Pradesh, India.
** Professor, Department of Electronics and Communication Engineering, NERIST (Deemed University), Arunachal Pradesh, India.
*** Associate Professor, Department of Electronics and Communication Engineering, Mizoram University (Central University), Mizoram, India.
Periodicity:September - November'2010
DOI : https://doi.org/10.26634/jele.1.1.1195

Abstract

Design of low power and high speed VLSI circuit has become a necessity for high performance portable devices operated by batteries. In this paper, power dissipation and switching speed of a 1- bit CMOS full adder in deep submicron and nanoscale technologies are analysed. Effects of variations in supply voltage and temperature on power dissipation and switching speed of a CMOS full adder are analysed. MICROWIND and DSCH 3.1 EDA tools are used for the schematic layout and simulation of a CMOS full adder in 0.4µm and 90 nm technologies using BSIM4 model.

Keywords

Power dissipation, Switching speed, Full adder, Temperature, Supply voltage.

How to Cite this Article?

Manish Kumar et.al (2010). Power Dissipation And Switching Speed Analysis Of A CMOS Full Adder In Deep Submicron And Nanoscale Technologies. i-manager’s Journal on Electronics Engineering, 1(1), 21-25. https://doi.org/10.26634/jele.1.1.1195

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