Table 1. Summary of Design Considerations
The aim of this paper is to promote intelligent road and vehicle safety systems in order to control the accident rates and vehicle damages by using Dedicated Short Range Communication (DSRC). The DSRC is of two types: automobile-toautomobile and automobile-to-roadside. In automobile-to-automobile, the DSRC has the ability of message sending and broadcasting among automobiles for safety issues and public information announcement. In this paper, the authors propose a complete simulation model of Dual Mode Logic, (DML) Technique. This method increases the hardware utilization rate from 57.14% to 100% for both FM0 and Manchester encodings being used for the Dedicated Short- Range Communication (DSRC) which is a budding technique to drive the smart transportation system into our daily life with low power digital system designs. The maximum operating frequency is 7GHz and 4GHz for Manchester and FM0 encoding. The on board power consumption is 1133 mW at 3.352 V for Manchester encoding and 1106 mW at 3.352 V for FM0 encoding. The presentation of this paper is evaluates 32nm CMOS technology by utilizing the design simulation Xilinx Vivado tools and layout simulation with extended DML Techniques using Microwind simulator. This paper not only provides a fully reused architecture but also exhibits high performance.
Now -a- days Automobiles play a significant role to promote haulage to the people. The usage of automobiles is growing every year, especially in metropolitan cities and towns. At the same time people face problems due to heavy traffic, meet accidents and lose their lives, and the vehicles get damaged due to collisions. To control accident rates, traffic grids, animal life and vehicle damages, a project was developed to provide smart, intelligent road and vehicle safety applications. Wireless communication is the fastest growing segment of communication industry. It has captured the attention of media and the imagination of the public. There are many new applications emerging in the wireless communication including automated highways and factories, smart homes, appliances and remote telemedicine. So the growth of the wireless systems coupled with the proliferation of laptop and palmtop computers as standalone systems is part of the larger networking infrastructure. In digital communications, to push the wireless services more data encoding schemes are required to send message from transmitter to receiver through channels. Based on the coverage area and interoperability the communication can be classified into three categories. Those are Short Range Communication, Near Field Communication and Far Field Communication.
Short Range Communication is again classified into two categories. They are Dedicated Short Range Communication [1] and Leased Short Range Communication. The operating frequency of DSRC is 5.8 and 5.9 GHz. The DSRC can be briefly classified into two types: automobile-to-automobile and automobile-toroadside. In the automobile-to-automobile, the DSRC has the ability of message sending and broadcasting among automobiles for safety issues and public information announcement [2], [3]. The safety messages include blind-spot, intersection warning, intercar distance, and collision-alarm. The automobile-to-roadside concentrate on the intelligent transportation service, such as electronic toll collection system.
Generally, in communication, the transmitted signal consists of arbitrary binary sequence for which it is difficult to obtain DC-balance. To overcome this limitation, DSRC standards generally adopt FM0/Manchester codes. The purposes of FM0/Manchester codes are to provide the transmitted signal with DC-balance and enhance the signal reliability. FM0/Manchester codes are widely adopted in encoding for downlink in DSRC. VLSI being a semiconductor technology, DSRC key ingredients are designed and verified using VLSI boards which consume small area, low power and exhibit high performance DSRC applications.
The VLSI architectures for FM0/Manchester encoders are developed as follows.
The literature [4] targets a VLSI architecture of a Manchester encoder for optical communications, implemented by 0.35-μm CMOS technology and its operating frequency is 1 GHz. The literature [5] further replaces the architecture of the switch in [4] by the NMOS device. It is realized in 90-nm, CMOS technology, and the maximum operation frequency is as high as 5 GHz. The literature [6] develops a high-speed VLSI architecture almost fully reused with Manchester and Miller encodings for RFID applications. This design is realized in 0.35-μm CMOS technology and the maximum operating frequency is 200 MHz. The literature [7] also proposes a Manchester encoding architecture for Ultra High Frequency (UHF) RFID tag emulator, realized into FPGA prototyping system, maximum operating frequency of this design is about 256 MHz. The similar design methodology is further applied to individually construct FM0 and Miller encoders also for UHF RFID Tag emulator [8]. Its maximum operation frequency is about 192 MHz. Furthermore, [9] combines Frequency Shift Keying (FSK) modulation and demodulation with Manchester code in hardware implementation. After analyzing all these literatures, the architecture is modeled with DML technique by using high performance simulation and synthesis tools and these design considerations are formulated in Table 1. The experimental results reveal that this design achieves an efficient performance compared with previous works.
Table 1. Summary of Design Considerations
The remainder of this paper is organized as follows. Section 1 describes the modeling of DSRC with DML technique. This reports the coding principles of both encoders, the proposed concepts of SOLS and DML techniques. Section 2 gives the simulation and synthesis results. Conclusion is given in the last section.
As mentioned earlier, the (SOLS) Similarity Oriented Logic Simplification has two methods: Area compact retiming and Balance logic operation sharing. The area compact retiming is used to condense the transistor counts. In the balance logic operation, sharing is used to unite the FM0 and Manchester encoding both having the following principle of operations and to enhance its physical parameters such as speed and utilization power, the Dual- Mode-Logic (DML) has been included in the physical layout design.
As shown in Figure1, the FM0 code consists of former half cycle of CLK, A, and later- half cycle of CLK, B. The FM0 encoding has the following three rules.
Figure 1. FM0 encoding
The Manchester encoding is realized with the XOR function for using the CLOCK and X. The clock always has evolution within the one cycle. And the process is shown in Figure2.
Figure 2. Manchester encoding
DML gates exist with two possible topologies: 1) Type A and 2) Type B, as shown in Figure 3. consequently. In the static mode of operation, the transistor M1 is turned off by smearing the high Clk signal for Type A and low Clk for Type B topology. So, the gates of both topologies operate alike the static logic gate, which now is a standard CMOS operation. To activate the gate in the dynamic mode, the Clk is allowed, allowing for two discrete phases: 1) pre- charge and 2) evaluation. Throughout the pre-charge phase, the output is charged to VDD in Type A gates and discharged to GND in Type B gates. Through evaluation, the output is assessed allowing the values of the gate inputs. DML gates demonstrate a very robust process in both static and dynamic modes in process variation at low supply voltages. The toughness in the dynamic mode is mainly achieved by the in-built active restorer (pull-up in Type A/pull-down in Type B) that also allows glitch sustaining, charge drip, and charge distribution. It is also seen that the suitable sizing methodology is the crucial factor to achieve faster operation in the dynamic mode. Differing to CMOS gates, every DML gate can be executed in two ways, only one of which is effective. The ideal topology is such that the pre-charge transistor is positioned in parallel to the stacked transistors, i.e., NOR in Type A is favored over NAND, and NAND in Type B is desired over NOR. In this event, the evaluation is executed through the parallel transistors and hence it is faster.
Figure 3. DML Topology
By considering all above mentioned principles the proposed scheme was verified with both front end and back end processes of VLSI technology. The implementation methodologies and recommendations are mentioned below.
This phase of implementation contains the following stages: Simulation using Xilinx 14.4 Vivado suite, Synthesis using Xilinx 14.4 XST and verification on Virtex – 5 FPGA board.
The intention of SOLS technique is to create a fully reused VLSI architecture for FM0 and Manchester encodings. The SOLS technique is classified into two parts: Area-compact retiming and Balance logic-operation sharing. The block diagram of the combined architecture is shown in Figure 4.
Figure 4. Proposed Architecture
The SOLS technique combines Manchester and FM0 encodings into fully reused hardware architecture. Evidently, the coding procedure of FM0 is more complex than that of Manchester. The data path of Manchester encoding is restricted to that of FM0 encoding. The operation frequency of Manchester encoding is also limited by that of FM0 encoding. The proposed work aims an efficient integration of hardware devices for Manchester encoding and FM0 encoding interms of process frequency and power consumption. Generally, more coding methods and hardware architecture can support more hardware devices required and this can be overcome with the proposed methodology.
The proposed scheme is described using Verilog HDL with RTL coding style and is simulated and synthesized with Xilinx tolls. The design is successfully verified on Virtex -5 FPGA board.
The logic functions of SOLS system can be realized by various logic families. Each logic family optimizes one or more electrical performance, such as area, power, or speed, from circuit topology perspective instead of architecture perspective. Since it is familiar that the key CMOS ingredients are Multiplexors and XNOR units which combine with each other to produce FM0 and Manchester encoding, hence the target blocks are designed with CMOS 32 nm technology as both units must combine with each other and balance each drawback by another one. The final target may suffer with switching delays and path sensitization delay. To overcome this, Dual Mode Logic has been proposed which drastically increases the speed of operation with reduced power consumption. The lay out designs of multiplexer and XNOR using DML technique are shown in Figure 5 and Figure 6 respectively.
Figure 5. Multiplexor with DML for DSRC system
Figure 6. XNOR design with DML for DSRC system
The Verilog RTL Description of the above article is simulated and synthesized using Xilinx14.4 (ISE-Simulator), and physical design layout results are observed separately with and without implementation of DML logic. It is noticed that at some instance of simulation the power and time delays are greatly improved with the implementation of Dual Mode Logic. The simulation and synthesized outputs are shown in Figure 7 and Figure 8 respectively. The adoption of FM0 or Manchester code depends on Mode and CLR. If Mode is equal to zero then the output is FM0 code where as if Mode is equal to logic one the result is Manchester code. This avoids the conflict between the coding mode selection and hardware initialization. Whether FM0 or Manchester code is adopted, no logic component of the proposed VLSI architecture is wasted. Every component is active in both FM0 and Manchester encodings. Therefore, the HUR rate of the proposed VLSI architecture is greatly improved.
Figure 7. Simulation output
Figure 8. Synthesized output
The Synthesis report is summarized in Table 2. The layout reports are summarized in Table 3. The on board power consumption for generation of FM0 code at various voltages are shown in Figure 9(a) and the power graphs are shown in Figure 9(b).
Table 2. Summary of Synthesis Report
Table 3. Summary of Layout Reports
Figure 9(a). Power consumption for FMO code
Figure 9(b). Power graph for FMO code
Finally the on board power consumption for generation of Manchester code at various voltages are shown in Figure 10(a) and the power graphs are shown in Figure 10(b).
The simulation and synthesis results show that the present VLSI Architecture using extended Dual Mode Logic Technique and SOLS technique improves the hardware utility rate and minimizes the input sensitization problems.
Figure 10(a). Power consumption for Manchester code
Figure 10(b). Power graph for Manchester code
This paper analyzes the complete VLSI modeling of fully reusable architecture for DSRC applications with DML method. The proposed work eliminates the problem of coding-diversity between FM0 and Manchester encoding and improves the hardware utilization. The maximum operating frequency is 7GHz and 4GHz for Manchester and FM0 encoding respectively. The on board power consumption is 1133 mW at 3.352 V for Manchester encoding and 1106 mW at 3.352 V for FM0 encoding. This paper has realized with Xilinx tools along with Virtex -5 FPGA and the relevant layouts are analyzed and various physical parameters are studied at 32 nm Technology. Such designs are suggested to exhibit a competitive performance with current work. The encoding capability discussed in this paper can fully support the DSRC standards of America, Europe and Japan. In India this concept was launched recently in Ahmadabad by Toyota for promoting Intelligent Transportation system. In future the DSRC may be implemented using high end FPGA protoptying environments and the applications may be extended to other contactless platforms like digital libraries, wall marts, retailers. This work is implemented in 32nm CMOS technology but as an advancement, in the ULSI technology the design may be implemented in 13nm.
The authors’ would like to thank Dr. V. Thrimurthulu, for his outstanding support and also they would like to especially express gratitude to EDUPLUS-IERC team for their technical advices.