The evolution of electronics, information technology and communication has mainly advanced due to progress in silicon based Complementary Metal Oxide Semiconductor (CMOS) technology. CMOS technology has progressed with double the number of on-chip transistors’ every generation, reducing the physical device size. A smaller sized transistor comes with an advantage of improved performance and packing density[1].

Continued scaling of CMOS technology has now reached to the nano scale dimensions, in order to achieve low standby power, low operating power and high performance requirements. But continuous scaling of transistor causes Short Channel Effects (SCEs) like Drain Induced Barrier Lowering (DIBL), Gate Induced Drain Leakage (GIDL), gate tunneling leakages and leakage current problems which are challenging. Due to this the transistor for the next generations has become a much more challenging task [2]. The reason is the ultra-steep doping profile requirements at the source-drain junctions. To overcome this problem new device architecture has been designed by several researchers of which some of the designed were based on Silicon- on- Insulator (SOI) MOSFET. By using SOI MOSFET frequency response will be improved because in SOI MOSFET there is reduction in parasitic capacitances, higher drive current, and a reduction in interconnect length [3]. Because of direct tunneling phenomenon the reduction of gate oxide, variation in drain current in saturation mode of MOSFET also occurs [4].

SOI technology has become most suitable technology in semiconductor industry. The first SOI MOSFET had been introduced in 1964 by Mueller and Robinson in 1987. It offered low capacitance so that it had improved speed. The advantages of SOI MOSFET is not only high speed and low power, but also in bearing high temperature and high voltage. In PD SOI MOSFET un-depleted neutral region exists at the bottom of SOI layer. Chen et al[5] proposed the Design of 65 nm partially depleted floating body SOI MOSFET for low off state leakage current and reduced latch-up problem. On the other hand, the FD SOI in the entire region of SOI layer is fully depleted. Roy et al [6] introduced a double gate fully depleted SOI MOSFET for low power and high voltage application. In this, coupling front gate and back gate investigates about the inference of the noise immunity and circuit reliability.

Another MOS device for low power application is Tunnel Diode Body Contact SOI MOSFET. J.Chen et al [7] introduced a Tunnel Diode Body Contact structure which showed the drain current behavior in saturation mode through suppressed Floating Body Effect.

SOI technology is a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing. SOI MOSFET reduces parasitic capacitances, thus improving the performance of bulk MOSFET. SOI-based devices differ from conventional bulk MOSFET. In SOI MOSFET the silicon junction is above an electrical insulator. Silicon dioxide is used to diminish the short channel effects in microelectronic devices. The insulating layer and topmost silicon layer may vary depending on the application. SOI devices are attractive for low-power high-speed VLSI applications because of their small parasitic capacitance [8]. Because of reduced parasitic capacitances its source and drain junction capacitances reduce so that SOI MOSFET provide better switching speed. This SOI MOSFET also reduces power and process variation effect by controlling threshold voltages through box layer[9]. Young et al. analyzed the SCE using a device simulator, and concluded that SCE is suppressed in thinfilm SOI MOSFET when compared to bulk MOSFET. In general, the thin-film SOI MOSFET has a higher immunity to SCE compared with bulk MOSFET. This may be due to the difference in source/drain junction depths between the two kinds of devices[10]. Since SOI technology has a number of advantages over conventional bulk MOSFET technology, like low junction capacitance, minimal leakage current, high gate controllability over the channel, and high robust breakdown voltage [11], [12], SOI MOSFET can be used to reduce the gate length of MOSFETs [13] and thus SOI MOSFET is useful in the scaling of modern Very Large Scale Integrated circuits. Due to presence of Buried-Oxide (BOX) layers there are few disadvantages present in SOI MOSFETs, such as low thermal conductivity[14],[15], trap state formation at the SOI/BOX interface [16[,17], and enhanced Drain-Induced Barrier Lowering (DIBL) [18],[19]

The SOI devices are of two types. PD SOI (Partially Depleted SOI) and FD SOI (Fully Depleted SOI) MOSFETs. The p-type film between the Gate Oxide (GOX) and buried oxide (BOX) is large in case of n-channel PD SOI MOSFET so the whole p region can't be covered fully by the depletion region. But the main problem that arises in PD SOI is Floating- body effect due to impact ionization. Holes generated near the drain accumulate in the body region, and then positively bias the body, thus reducing threshold voltage. This positive bias effect leads to lowering of threshold voltage for all gate lengths, including rather long gates such as 2µm. The hole generation rate due to impact ionization increases as gate length decreases under a fixed ratio of drain to source voltage. This effect mainly occurrs in Partially Depleted (PD SOI) n-MOSFET and results in so-called Floating-Body Effect[20].

Fully depleted SOI MOSFET is also called extremely thin MOSFET because in this, p-type film between gate oxide and buried oxide is very thin as compared to PD SOI MOSFET. Fully depleted Extremely Thin SOI (ETSOI) is considered as one of the main options for continued MOSFET scaling in 22-nm technology node and beyond [21], [22]. The cross sectional view of FD SOI MOSFET is shown in Figure 1. Random Dopant Fluctuation (RDF) is another problem with bulk MOSFET which result in threshold voltage variation and it increases with MOSFET scaling[23]. The threshold voltage variation due to RDF mainly depends upon MOSFET parameters like channel length, doping, and oxide thickness [24]. The effect of these parameters are also studied for FD SOI MOSFET. FD SOI MOSFET shows better short channel control without need for channel doping. This shows that FD SOI MOSFET provides better control of threshold voltage variation due to random dopant fluctuation [25]. The problem of Floating-Body Effect in PD SOI MOSFET is only because of impact ionization phenomenon accumulation in neutral body until a steady state is reached by diode recombination and generation mechanism, which causes reduction in threshold voltage and as a result a kink in the output characteristic (a spike in output conductance) [26]. But in FD SOI MOSFET due to smaller well majority carrier accumulation and reduced potential variation between source and body floating body effect is well suppressed [27]. H.S Wong et al [29] proposed a thin body FD SOI MOSFET in which source/drain current flow was only in the region that is close to the gate. This provides better gate control. Since in this structure channel is not heavily doped, it avoids the problem of mobility degradation due to impurity scattering and this structure also provides better control of threshold voltage variation due to number of dopant atoms in the channel region. Y.K Choi et al[30] demonstrated a thin-body-on insulator with raised source and drain region to avoid the high series resistance problem. A thin source and drain region causes problem of high series resistance but the parasitic capacitances between raise source/drain and gate are the main problem for this structure and this affects the device speed and power consumption. J.Kedzierski et al [31] proposed another structure for reducing source and drain resistance in thin film FD SOI MOSFET. This structure consists of metal (silicide) source and drain. But this device structure is more preferable to be used in accumulationmode because schottky barrier should be low for better ohmic contact between source/drain and channel. Schottky barrier varies with applied gate bias in inversionmode, so this device is mainly used in accumulationmode where surface potential remains constant when an accumulation channel is created.

A. Vendroorem et al [32] analyzed that if buried oxide permittivity reduces there is improvement in DIBL effect. This is only because of reduced electric field penetration into buried oxide from the drain. T.Ernst et al [33] proposed a new structure to avoid the problem of penetration of electric field line from drain into channel region. For this a ground plain formed in silicon substrate underneath the buried oxide was used. This device structure improves short channel effect and sub threshold slope.

Several researchers proposed different structures to suppress the problem of Floating-Body Effect in PD SOI MOSFET such as body contact with T-gate [34], I-gate [35], and body contact SOI [36]. But these structures have few limitations like larger device area and lower effective device width [37]. Jing Chen et al [7] proposed a new structure called as Tunnel Diode Body Contact SOI MOSFET to suppress the Floating Body Effect in PD SOI MOSFET. The cross-sectional View of TDBC SOI MOSFET is shown in Figure 2. In this structure an Esaki Tunnel Diode is introduced in the source region so that the hole accumulation due to floating body effect in p+ region is released by tunneling phenomenon. This structure reduces not only the Floating-Body Effect but also improves short channel effect and Kink-free environment. This device increases the drain breakdown voltage and due to this there is no dependency of gate length and sub-threshold swing. Mohammad.K Anvarifard et al [40] analyzed that Hysteresis Effect appears in conventional Floating Body PD SOI MOSFET. Due to this effect a positive peak at low gate voltage and negative peak at high gate voltage occur in drain current. But this effect is well suppressed in Tunnel Diode Body Contact SOI MOSFET. K.Lu et al [38] analyzed a PD SOI MOSFET with TDBC structure. This structure provides better frequency performance as compared to Body Contact MOSFET. J.Luo et al[39] proposed a TDBC structure that reduces back channel leakage. This leakage is caused by radiation induced charge trapping in buried oxide. Mohammad. K Anvarifard et al [34] proposed a modified Dual Tunnel Diode (DTD-SOI) Body Contact SOI MOSFET. In this structure a heavily doped P-type region is placed between source region and channel region and also beneath the source region and portion of the channel region. This region is called as P-type L-shape trench. Two Tunnel Diodes created between source region and P-type trench region thus accumulates holes in DTD-SOI structure easily released by Tunneling current of Two Tunnel Diodes. Due to this kink delayed, and higher drain voltage occurs which reduces the Floating Body Effect at operating voltage.

Figure 1. Cross sectional view of FD SOI MOSFET [28]

Figure 2. Cross sectional schematic of TDBC SOI MOSFET [7]

This paper concludes that a thin film SOI MOSFET provides higher immunity to short channel effects DIBL effect, gate induced drain leakage and gate tunneling leakage as compared to conventional bulk MOSFET. Several advantages of SOI MOSFET make it useful in scaling of modern very large scale integrated circuits. Strengths and weaknesses of different FD SOI approaches have been discussed in this paper. FD SOI has certain advantages over PD SOI MOSFET as there is no floating body effect and random dopant fluctuation. This paper also concludes that TDBC SOI MOSFET provides better immunity to Floating Body Effect and short channel effect in PD SOI MOSFET as compared to FD SOI MOSFET.