With the concept of substantial energy reduction concept, we achieved the sub-threshold operation as an evidence by the minimum energy point theory ( Calhoun & Chandrakasan, 2004), and VLSI logic families operating under the threshold voltage (V ) is favored for T wearable/implantable biomedical systems that requires low-to-moderate computation speed with stringent power budget. However, the overdrive voltage continues to decrease and dramatically worsens the device susceptibility in the form of delay and noise margin due to voltage, and temperature variations ( Tajalli & Leblebici, 2011). This inevitably leads to suboptimal performance in terms of power, delay, area, and even logic failure in the worst case. Formally, a balanced Pull-Up (PU) and Pull-Down (PD) network approach is preferable in defining the logic cell design, which is important for the concept of sub threshold cell design to have similarities between PU/PD driving capability ( Reynders & Dehaene, 2012; Alioto, 2010). Even though the above process can be readily achieved by either upsizing length/widths of the pMOS in the PU network or stacking the variables for nMOS in the PD network, the area overhead can lead to extra loading and excessive leakage power, and a sub-optimal energy efficiency with an identical total width as a unbalanced one (Figure 1). In Hwang et al. (2007), a balanced PU/PD network is achieved using a body biasing scheme. However, this requires extra monitoring blocks and the occurrence of considerable area and power penalties. In Liu et al. (2013), the statistical distribution of the drain–source current, rather than the current itself is investigated to achieve the balanced networks. In Kim et al. (2007), the Reverse Channel (RSC) effect is used for the device for optimization by increasing the length of the channel to have an optimal threshold voltage (V ) and T higher driving capability. Yet, the RSC effect is not readily applicable to different technological nodes.
1. Design and Structure
1.1 Single-Stage Gates Design
In general there are Single-mode gates like INV, NOR, and NAND, which are scaled with reference to the standard inverter ( Alioto, 2010). The total energy consumption by an arbitrary circuit is defined as in Calhoun and Chandrakasan (2004).
These basic gates are designed by Mentor Graphics tool. The basic inverter is designed with pMOS and nMOS transistors as shown in Figure 1(a). In this we have to create the universal gates, which are NAND gate and NOR gate which are show in Figure 1(b) and Figure 1(c). In the gates, we observed the saving of power dissipation and area.
1.2 Multistage Gates Design
For multistage gates, such as XOR and XNOR, a logical effort similar to single-stage gates can be utilized to capture the signal propagation delay as it gives the result of different logic topologies as shown in Figure 2. The logical effort is done for a specific logic gate. The specific logic gates are XNOR Conventional and XNOR Pass transistors as shown in Figures 2 and 3 respectively.
Figure 2. XNOR Gate Conventional
Figure 3. XNOR Gate Pass Transistor
2. Existing D Flip Flop
D-flip flop of 18 transistors are designed with the logic gates. For 18 transistors of D-flip flop, power and area used is decreased. 16 tap 8 bit 16 tap is 16 D-flip flop and 16 adders and 16 multiplier are used and 8 bit input is given and this capability is difficult to be clarified and characterized. Here, the structure is taken as a standard consideration for transistor scaling, with increased driving capability to obtain a comparable Pull-up and Pull-down propagation delay with respect to basic considered logic cell.
NAND3 and NOR3 provide the most rigorous Pull-up and Pulldown propagation delays, respectively, and their butter-fly plots ( Kwong & Chandrakasan, 2006) are used for characterizing their noise margins, and serve as a reference for validating the meta stability of the remaining gates. The static noise margin is defined by the largest inscribed square, which can indraw in the butterfly plots, and then the noise margin is the diagonal of those squares. Figure 5 shows the corresponding 5-k Monte Carlo simulation results indicating that the gate under test has sufficient noise margin to tolerate the worst case transition slope. Figure 4 shows that the worst case noise margin is stringent with NOR3 at 0.99 um, and the logic function is approaching the point of breakdown. In case of the occurrence of negative noise margin, the power supply voltage can be increased to guarantee an enough noise margin, as shown in Figure 4 and Table 1 shows D-flip flops for different values.
Figure 4. D Flip Flop
Figure 5. 10 Transistors D-Flip Flop
Table 1. D Flip Flops for Different Values
3. Proposed D-Flip Flop
The sequential logic elements, such as latch and flipflop, are indispensable to provide storage logic function. To ensure sub threshold operation with reduced power consumption, an 18-transistor flip-flop based on logical effort is derived and shown in Figure 7.
The butterfly plot is used to verify the meta stability and data retention capability. The proposed D flips-flop (DFF) is implemented with 18 transistors using the unbalanced technique and compared with the conventional balanced 10-transistors (Figure 5) and transistors (Figure 6) and refer Table 2 for comparison of D-flip flops.
Figure 6. 5 Transistors D-Flip Flop
Figure 7.16 Tap D Flip Flop
Table 2. Comparison of D Flip Flops
Conclusion
This paper implemented D-flip flop with 10 transistors and 5 transistors using 130 nm technology. When implementing the inverse narrow width technique, the width of transistors varies from 0.22 mm to 0.99 mm. Corresponding results are power dissipation, rise time, delay and fall time decrease, when compared with the other different width results on parameters such as energy optimization. By using this technology, logic circuits can be designed for the reduction of glitches or noise in signals such as error voltage signal. By comparing the existing paper with 18 transistors using 180nm technologies, the authors designed a 16 tap D-flip flop of 18 transistors, 10 transistors and 5 transistors. From that, it was observed that low power dissipation of 1.24 nW and delay 50.34 ps for 16 tap D-flip flop of 5 transistors implemented for an application is 4 bit shift register.
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