This paper is mainly focused to design modern semiconductor memory. Now-a-days, the conventional memory design should be implemented in CAD tools. While, the size of the memories that can be generated are still limited to some degree. The proposed memory system will use automatic synthesis approach. The bit density reduction and minimum chip area will be achieved by Reconfigurable CMOL memory array (bad bit omission), combined with error correction code techniques, in Reconfigurable terabyte-scale, hybrid Nano-Device /semiconductor memories, as a function of the nano-device fabrication yield and the micro-to-nano scale ratio. The results prove that by using the best (but hardly practicable) reconfiguration and block size optimization, CMOL memories with a pitch ratio of 10 should overcome purely semiconductor memories in useful bit density if the fraction of spoiled nano-devices is beneath ~15%, while in order to get an order-of-magnitude , the advantage in density, and the number of bad devices have to be below ~2%. For the simple 'Repair Most' technique of bad bit omission, complemented with the Hamming-code error correction. When applied to CMOL memories, the automatic synthesis technique reduces the chip area 'swelling' to just 40% at as many as 0.1% of bad devices. In addition, power and speed of the CMOL memories are estimated. The proposed system determines that Nano-devices are well suited in modern memory system.