References
[1]. L.Bisdounis, D.Gouvetas and O.Koufopavlou, (1998).
“A Comparative Study of CMOS Circuit Design Styles for
Low Power High-speed VLSI circuits”. Int. J. of Electronics,
Vol. 84, No.6, pp 599- 613.
[2]. Kaushik Roy and Sharat C Prasad, (2011). Low Power
CMOS VLSI Circuit Design. Wiley India Publication.
[3]. R. Shalem, E. John, and L.K.John, (1999). “A Novel
Low-Power Energy Recovery Full Adder Cell”. In Proc.
Great Lakes Symp. VLSI, Feb. 1999, pp.380-383.
[4]. A.Sharma, R Singh and R. Mehra. “Low Power TG Full
Adder Design Using CMOS Nano Technology”
[5]. T. Esther Rani, M. Asha Rani and Dr. Rameshwar rao,
(2011). “Area Optimized Low Power Arithmetic and Logic
Unit” 978-1-4244-8679 3/11/ IEEE.
[6]. Morgenshtein, A. Fish and A. Wagner, I.A. (2002).
Gate-Diffusion Input (GDI) – A Technique for Low Power
Design of Digital Circuits: Analysis and Characterization.
In: ISCAS, USA.
[7]. K-H Cheng and C-S Huang, (1999). "The Novel
Efficient Design of XOR, XNOR Function For Adder
Applications". In 6th IEEE International Conference on
Electronics. Circuits and System, Vol. 1.
[8]. R. Uma, Vidya Vijayan, M. Mohanapriya, Sharon Paul, Area, Delay and Power Comparison of Adder Topologies.
[9]. R.Uma and P. Dhavachelvan, (2012). “Modified Gate
Diffusion Input Technique: A New Technique for Enhancing
nd Performance in Full Adder Circuits” 2 International
Conference on Communication, Computing & Security
[ICCCS 2012].
[10]. J. Clerk Maxwell, (1892). A Treatise on Electricity and
rd Magnetism, 3 Ed., Vol. 2. Oxford: Clarendon, pp. 68-73.
[11]. S. Salehi, and R. F. DeMara, (2015). “Energy and Area
Analysis of a Floating-Point Unit in 15 nm CMOS Process
Technology”. in Proceedings of IEEE SoutheastCon 2015
(SECon-2015), Fort Lauderdale, FL, April 9 - 12.
[12]. Roohi, R. F. DeMara, and N. Khoshavi, (2015).
“Design and Evaluation of an Ultra-Area-Efficient Fault-
Tolerant QCA Full Adder”. Microelectronics Journal, Vol.
46, No. 6, pp. 531-542.
[13]. M. Alawad, Y. Bai, R. F. DeMara, and M. Lin, (2014).
“Energy-Efficient Multiplier-Less Discrete Convolver
through Probabilistic Domain Transformation”. in
nd Proceedings of 22 ACM/SIGDA International Symposium
on Field-Programmable Gate Arrays (FPGA-14), pp. 185-
188, Monterey, California, USA, February 27-28.
[14]. N. Imran, R. F. DeMara, J. Lee, and J. Huang, (2014).
“Self-adapting Resource Escalation for Resilient Signal
Processing Architectures”. The Springer Journal of Signal
Processing Systems (JSPS), Vol. 77, No. 3, pp. 257-280.
[15]. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn,
and D. Ferguson, (2002). “NULL Convention Multiply and
Accumulate Unit with Conditional Rounding, Scaling, and
Saturation”. Journal of Systems Architecture, Vol. 47, No.
12, pp. 977 - 998.
