i-manager Publications

Design of Hybrid Full Adders for Power Minimization and High Speed using XOR and XNOR Gates

Pramod Kumar Aylapogu*

Department of Electronics and Communication Engineering, Vardhaman College of Engineering (Autonomous), Hyderabad, Telangana, India.

Periodicity:September - November'2019
DOI : https://doi.org/10.26634/jele.10.1.16227

Abstract

In recent trends, power optimization and improvement of speed are the key researches in the VLSI circuit design. This paper presents an advanced hybrid full adder. Most of the adder has a powerful impact on the overall performance of the system. The modern design is correlated with some actual designs to enhance performance parameters such as power utilization, delay, and PDP. In the proposed circuit, the power delay product is maximum of 96.8% with respect to Complementary Metal-Oxide Semiconductor (CMOS) at minor frequency. The power utilization is increased at a slow rate in contrast to other adders with increase in frequency. The simulations are drifting out on Cadence Virtuoso at 130 nm. By correlating with the previous Full Adder (FA) designs, the present operation was found to offer a powerful improvement in terms of speed and power.

Keywords

CMOS Logic, Power Consumption, Delay, PDP, ALU, Cadence Virtuoso.

How to Cite this Article?

Aylapogu, P. K. (2019). Design of Hybrid Full Adders for Power Minimization and High Speed using XOR and XNOR Gates. i-manager's Journal on Electronics Engineering, 10(1), 22-28. https://doi.org/10.26634/jele.10.1.16227

References

[1]. Aranda, M. L., Báez, R., & Diaz, O. G. (2010, September). Hybrid adders for high-speed arithmetic circuits: A comparison. In 2010 7^th International Conference on Electrical Engineering Computing Science and Automatic Control (pp. 546-549). IEEE. https://doi.org/10.1109/ICEEE.2010.5608566

[2]. Chang, C. H., GU, J., & Zhang, M. (2005). A review of 0.18-μm full adder performances for tree structured arithmetic circuits. IEEE Transactions Very Large Scale Integration (VLSI) System, 13(6), 686–695. https://doi.org/ 10.1109/TVLSI.2005.848806.

[3]. Deb, P., & Majumder, A. (2016, March). Leakage reduction methodology of 1-bit full adder in 180nm CMOS technology. In 2016 3^rd International Conference on Devices, Circuits and Systems (ICDCS) (pp. 199-203). IEEE. https://doi.org/10.1109/ICDCSyst.2016.7570636

[4]. Goel, S., Elgamel, M. A., & Bayoumi, M. A. (2003, September). Novel design methodology for high-performance XOR-XNOR circuit design. In 16^th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. (pp. 71-76). IEEE. https://doi.org/ 10.1109/SBCCI.2003.1232809

[5]. Goel, S., Kumar, A., & Bayoumi, M. A. (2006). Design of robust, energy-efficient full adders for deepsubmicrometer design using hybrid-CMOS logic style. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(12), 1309-1321. https://doi.org/10.1109/ TVLSI.2006.887807

[6]. Pattnaik, S. K., Nanda, U., Nayak, D., Mohapatra, S. R., Nayak, A. B., & Mallick, A. (2017, May). Design and implementation of different types of full adders in ALU and leakage minimization. In 2017 International Conference on Trends in Electronics and Informatics (ICEI) (pp. 924- 927). IEEE.. https://doi.org/10.1109/ICOEI.2017.8300841

[7]. Rabaey, J. M., Chandrakasan, A. P., & Nikolic, B. (2002). Digital Integrated Circuits (2^nd Ed). Delhi, India: Pearson Education, Retrieved from http://bwrcs.eecs. berkeley.edu/Classes/IcBook/tocv3.pdf

[8]. Radhakrishnan, D. (2001). Low-voltage low-power CMOS full adder. IEE Proceedings-Circuits, Devices and Systems, 148(1), 19-24. https://doi.org/10.1049/ipcds: 20010170

[9]. Shams, A. M., Darwish, T. K., & Bayoumi, M. A. (2002). Performance analysis of low-power 1-bit CMOS full adder cells. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(1), 20-29. https://doi.org/10.1109/ 92.988727

[10]. Shin, K., & Kim, T. (2004). Leakage power minimisation in arithmetic circuits. Electronics Letters, 40(7), 415-417. https://doi.org/10.1049/el:20040282

[11]. Sudsakorn, A., Tooprakai, S., & Dejhan, K. (2012). Low power CMOS full adder cells. In 9^th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, (pp. 1-4). https://doi.org/10.1109/ECTICon. 2012.6254174

[12]. Tung, C. K., Hung, Y. C., Shieh, S. H., & Huang, G. S. (2007, April). A low-power high-speed hybrid CMOS full adder for embedded system. In 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems (pp. 1-4). IEEE. https://doi.org/10.1109/DDECS.2007.4295280

[13]. Vesterbacka, M. (1999, October). A 14-transistor CMOS full adder with full voltage-swing nodes. In 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No. 99TH8461) (pp. 713-722). IEEE. https://doi.org/10.1109/SIPS.1999.822379

[14]. Wairya, S., Singh, G., Nagaria, R. K., & Tiwari, S. (2011, December). Design analysis of XOR (4T) based low voltage CMOS full adder circuit. In 2011 Nirma University International Conference on Engineering (pp. 1-7). IEEE. https://doi.org/10.1109/NUiConE.2011.6153275

[15]. Zimmermann, R., & Fichtner, W. (1997). Low-power logic styles: CMOS versus pass-transistor logic. IEEE Journal of Solid-state Circuits, 32 (7), 1079-1090. https://doi.org/10.1109/4.597298

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Design of Hybrid Full Adders for Power Minimization and High Speed using XOR and XNOR Gates

Abstract

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