An Intelligent Base Link Recovery Management and Path Stability in Clustered Randomly Distributed Mobile Ad Hoc Networks
A High-Performance Dual Classifier Based Packet Classification Engine on FPGA
An Overview of Smart Grid Smart Meters with Fault Detection
Shopping Trolley for Automated Billing System with Pick and Place Mechanism using Image Processing
Flexing Frontiers: Pioneering Advances in Biosensors for Instant Health Insights
The Impact of Substrate Doping Concentration on Electrical Characteristics of 45nm Nmos Device
A Study on Globally Asynchronous and locally Synchronous System
Performance Analysis of Modified Source Junctionless Fully Depleted Silicon-on-Insulator MOSFET
Method of 2.5 V RGMII Interface I/O Duty Cycle and Delay Skew Enhancement
Automatic Accident Detection and Tracking of Vehicles by Using MEMS
Efficient Image Compression Algorithms Using Evolved Wavelets
Computer Modeling and Simulation of Ultrasonic Signal Processing and Measurements
Effect of Nano-Coatings on Waste-to-Energy (WTE) plant : A Review
ANFIS Controlled Solar Pumping System
An Intelligent Base Link Recovery Management and Path Stability in Clustered Randomly Distributed Mobile Ad Hoc Networks
The conventional Voltage-Controlled Oscillators (VCO) are impractical to generate the full swing outputs and wide range of tuning, because the conventional differential VCO's are used as the tail current sources. The full swing, wider tuning range and low voltage VCO's are widely used in every applications. This paper proposes a new CMOS VCO. The proposed VCO uses a single-ended delay cell and achieves the widest tuning range, speed in operation and improved noise performance. The supply voltage used in the proposed system is 1.2V. Moreover, it's simple topology features multiple advantages like area and linear frequency-voltage characteristics. The proposed system has achieved a very wide range of tuning and good noise performance compared to the conventional VCO's. The topology can be used in pulse based applications.
To represent very large or small numbers, a wide range of fixed point representation is required, which is no longer effective. These numbers can be represented based on the IEEE-754 standard. This paper presents the designing of an inexact floating-point adder/subtractor which can perform addition, and subtraction operations. These operations are performed based on the single-precision floating-point format that uses IEEE754-2008 standard. An inexact circuit offers an approach that reduces both static and dynamic power for error tolerant applications. The normalization and rounding operations are the related operations, which are dealt with in terms of inexact computing. The main objective of this design is to decrease the area and increase the speed. The results of this inexact floating-point unit are below 30% error deviation, which is acceptable. The inexact floating point Adder/subtractor is modeled in VHDL and the simulation results are obtained from Xilinx ISE 14.5.
The Adaptive FIR filters plays an important role in Digital Signal Processing. This paper presents a Novel Design of efficient Adaptive FIR filters by using A1CSAS. Many of the devices are powered by batteries. Therefore, there is a need for an excellent compromise between performance and power consumption. Usually, either delay or power is prioritized in this paper. These requirements are conflicting normally; when one requirement is optimized the other is affected. The delay is reduced by using carry select adder with add one select block (A1CSAS) in the inner product of the Adaptive FIR filter. Adaptive FIR filters are performed by Distributed Arithmetic process because it is an easy and simple method. Inner products in the DA table are calculated by using Distributed Arithmetic process. The add one carry select adder (A1CSA) is replaced by the proposed A1CSAS in order to the reduce the delay, and time complexity and to improve the speed. A1CSAS is better than A1CSA in terms of LUT's and Delay. The main aim of the project is to maintain a simplicity construction and reduce LUT's and Delay. The simulation results are obtained by using Xilinx ISE 14.5 version tool.
Iterative methods are the basic building blocks of communication systems and represent a dominating part of the system. So, it is necessary for the careful design of the system for optimal performance. The most computationally expensive operations in the iterative methods are the matrix-vector multiplications. Therefore, it is important to reduce the number of matrix-vector multipliers in the design to reduce the hardware consumption. In this paper, the authors have proposed a design of matrix-vector multiplier that can be used to implement the widely adopted iterative methods. By using Brent Kung adder, the computational performance is increased by reducing the hardware consumption. The proposed design uses the sparse structure of the matrix and the spreading code matrices have equal magnitude entries. The design and simulation results are promising and are shown to satisfy the most modern communication system requirements.
This paper proposes a simple and efficient Modular Multiplication algorithm. Montgomery modular multipliers can be implemented accordingly. Based on the Montgomery technique, both SCS and FCS are used by the Carry save format and also the modified SCA. The proposed SCS have used CCSA. To increase the performance of the cryptosystem, the modular multiplication is interleaved by serial and parallel radix-4 modular multipliers and also the same for normal multiplication. By comparing this technique, critical path and clock cycles are reduced. Now these techniques are used in Verilog HDL Virtex-3E using Xilinx ISE 14.5 design suite.
This paper explains the implementation based on adaptive filter algorithm with shadow technique, which belongs to the class of LMS algorithm on FPGA. The objective of this paper is to cancel out additive noise due to the effect of environmental conditions in the communication system. The additive noise is one of the major problems in the communication, especially in the digital electronic circuits design these days. Generally, the coefficient of filter updation is not in a basic filter time to time, as it may be an effect on the desired information. By updating coefficient of filter time to time, this problem could be eradicated and by increasing the number of iterations for the filtering process, it would give an efficient result. The popular method used to cancel out the additive noise in the communication systems is the Least Mean Square (LMS) algorithm. Here, a novel shadow based technique is employed in fixed LMS adaptive filter for improving the spectral characteristics like Side Lobe Attenuation (SLA), Main Lobe Width (MLW), Side Lobe Fall of Ratio (SLFR) of the filter by changing the feedback factor 'β'. In this project, it is found that the performance of shadow based fixed LMS is improved when compared to the existed fixed LMS in terms of signal-to-noise ratio (SNR) and Mean Squared Error (MSE) done with the help of MATLAB tool, and this proposed project was implemented on FPGA with utilization of minimum number of logic gates, flip flops, LUT's, and registers that are operated at maximum frequencies. This paper also compares the number of flip flops, logic gates, LUT's, and registers utilized for different resources in the family of FPGA. In real time applications, the adaptive filter algorithm implementation on FPGA plays a crucial role, especially in the DSP processors for effective communication. By introducing the concept of shadow technique in the adaptive filtering, the additive noise would be suppressed in the communication systems. The core FPGA is designed such that, it can be implemented in any brand of SoPC. In this paper, SPARTAN 3E and Vertex 4 are the application platform of FPGA. The achieved results gives an improvement in area resource utilization, convergence rate, speed, and performance in design pure LMS hardware core. Implementing the LMS adaptive filter algorithm on FPGA is achieved in VERILOG hardware description languages.
