i-manager's Journal on Electronics Engineering (JELE)


Volume 6 Issue 2 December - February 2016 [Open Access]

Article

RFID Technology for Biomedical Applications: State of Art and Future Developments

Roberto Marani* , Anna Gina Perri**
* Researcher, Consiglio Nazionale Delle Ricerche, Istituto di Studi sui Sistemi Intelligenti per l'Automazione (ISSIA), Bari, Italy.
** Full Professor, Electronics and Head of Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari, Italy.
Marani, R., and Perri, A.G. (2016). RFID Technology for Biomedical Applications: State of Art and Future Developments. i-manager's Journal on Electronics Engineering, 6(2), 1-12. https://doi.org/10.26634/jele.6.2.3761

Abstract

In this paper some of the possible applications in the biomedical field of the RFID technology are presented, giving an idea of the wide range of advantages that RFID devices are able to provide. In particular, those aspects of RFID technology were examined, which make possible the realization of miniaturized devices, implantable in the human body and powered from the outside, and can monitor the biological functions of individuals or even enable the therapy of diseases. Moreover, some aspects that need to be improved in the future research works are discussed such as the biocompatibility of the material for the implantable devices, the long-term exposure of the human body to electromagnetic fields, the interference caused by surrounding metallic parts, the attenuation of RF signals at particularly high frequency values and the implementation of a safe communication channel in order to guarantee the privacy of the individual.

Research Paper

Trichotomous Visual Analytics [TVA]: Visual StatisticalCumulative Data Analysis via the Tri–Squared Calculator ADigital Instrument Designed to Present theOutcomes of the Tri–Squared Test

James Edward Osler II*
Faculty Member, Department of Curriculum and Instruction, North Carolina Central University (NCCU) School of Education, USA.
Osler, J. E., II. (2016). Trichotomous Visual Analytics [TVA]: Visual Statistical © Cumulative Data Analysis via the Tri–Squared Calculator A Digital Instrument Designed to Present the Outcomes of the Tri–Squared Test. i-manager's Journal on Electronics Engineering, 6(2), 13-21. https://doi.org/10.26634/jele.6.2.3762

Abstract

This paper presents an innovative digital instrument the Tri–Squared Calculator © that uses the novel Trichotomous Visual Analytics [TVA] as a supportive research model for traditional confirmatory trichotomous statistical analyses. This research adds to the publication entitled, “Trichotomous Exploratory Data Analysis [Tri–EDA]: A Post Hoc Visual Statistical Cumulative Data Analysis Instrument Designed to Present the Outcomes of Trichotomous Investigative Models” published in the imanager's Journal on Instrumentation and Control Engineering. This narrative provides an epistemological rational for the use of “Trichotomous Exploratory Data Analysis” and other trichotomous statistical analytical models for the in–depth analysis of the transformative process of qualitative data into quantitative outcomes through the Tri–Squared Test. The Tri–Squared Test was first introduced in the i-manager’s Journal on Mathematics, and further detailed in the Journal on Educational Technology, Journal on School Educational Technology, and in Journal on Educational Psychology. TVA is used in Tri–Exploratory Data Analysis as a series of graphical and visual statistical models that are a part of the Tri–Squared Calculator ©. The Tri–Squared Calculator © digital instrument was created, designed, and developed by the author to quickly calculate and report Tri–Squared Test outcomes. It also allows the researcher to rapidly check the validity and reliability of Tri–Squared Test results. This is a novel approach to advanced statistical Tri–Squared modeling and reporting. It adds a potent new tool to the mixed methods approach of the trichotomous research design (that intrinsically involves the holistic trichotomous combination and comparison of qualitative and quantitative data outcomes).

Research Paper

Voltage Mode Second Order Notch/All - PassFilter Realization Using OTRA

Rashika Anurag* , Neeta Pandey**, Rohan Chandra***, Rajeshwari Pandey****
* Associate Professor, Department of Electronics and Communication Engineering, JSS Academy of Technical Education, NOIDA, India.
**_**** Associate Professor, Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India.
Anurag, R., Pandey, N.,Chandra, R., and Pandey, R. (2016). Voltage Mode Second Order Notch/All - Pass Filter Realization Using OTRA. i-manager's Journal on Electronics Engineering, 6(2), 22-28. https://doi.org/10.26634/jele.6.2.3763

Abstract

This paper presents a Second Order Notch/All pass filter based on Operational Transresistance Amplifier (OTRA). It uses two OTRA's and five resistances. To add electronic tunability, the filter uses a capacitor array that can be controlled by switches. The switches are also used to provide inverting and non inverting Notch/All pass as response. This adds flexibility in phase response of all pass filter. The notch/all pass configuration is a modified extension of the Delyiannis-Friend circuit. Through the addition of a second active block which basically acts as a summer for the input voltage and the output of the first OTRA block. The functionality of the proposed filters is verified through SPICE simulations using CMOS based implementation of OTRA. The power supply for the implementation is 1.5V and is based on 0.5 submicron technology.

Research Paper

Comparative Analysis and FPGA Implementationof Vedic and Booth Multiplier

Parul Agrawal* , Rahul Sinha**
* PG Scholar, Department of Electronics and Telecommunication, C.S.I.T, Durg, India.
** Assistant Professor, Department of Electronics and Telecommunication, C.S.I.T, Durg, India.
Agrawal, P., and Sinha, R. (2016). Comparative Analysis and FPGA Implementation of Vedic and Booth Multiplier. i-manager's Journal on Electronics Engineering, 6(2), 29-35. https://doi.org/10.26634/jele.6.2.3764

Abstract

The digital computing systems like mathematical co-processors, micro-processors, digital filters must be highly efficient in terms of computational time. The most fundamental operation in any computing systems is multiplication. The multiplier should therefore employ minimum processing time by the use of high speed adders. This paper describes the design of Vedic Multiplier using Kogge Stone Adder (the fastest Parallel Prefix Adder) and Booth Multiplier (based on two's complement notation). The two designs have been compared based on delay, levels of logic, number of slices, and memory usage. Based on the synthesis report obtained, the delay in Booth Multiplier has been found to be very less compared to Vedic Multiplier however, during simulation in Booth Multiplier the response to the inputs is not instantaneous, but there is a large amount of wait period in getting the output as the count signal increments in the sequential circuit which is not the case with Vedic Multiplier (Combinational Circuit). This showed that the Booth Multiplier is slower compared to Vedic Multiplier. The two designs have been implemented in Xilinx ISE 14.4 for the family of devices Spartan 6 with the device name Xc6slx45, package csg324,and speed grade of -3.

Research Paper

A Novel Multilevel Inverter with Minimum Switches

Manjunatha B.M.* , Ashok Kumar D.V.**, Vijay Kumar M.***
* Assistant Professor, Department of Electrical and Electronics Engineering, Rajeev Gandhi Memorial College of Engineering and Technology, Nandyal, Andhra Pradesh, India.
** Dean and Professor, Department of Electrical and Electronics Engineering, Rajeev Gandhi Memorial College of Engineering and Technology, Nandyal, Andhra Pradesh, India.
*** Professor, Department of Electrical and Electronics Engineering, Jawaharlal Nehru Technological University, Anantapur, Andhra Pradesh, India.
Manjunatha, B.M., Kumar, D.V.A., and Kumar, M.V. (2016). A Novel Multilevel Inverter with Minimum Switches. i-manager's Journal on Electronics Engineering, 6(2), 36-41. https://doi.org/10.26634/jele.6.2.3766

Abstract

This paper presents an unique three phase seven level inverter with reduced number of switches. Multilevel Inverters (MLI) are used in high power and high voltage applications as they are capable of producing multiple levels in output voltage with reduced THD. To reduce THD further, the number of levels in the output voltage has to be increased, which is directly associated with the number of switches required. To accomplish this, the conventional MLI experiences complexity in control, number of required DC sources, size, switching losses and cost of overall system increases. The proposed topology overcomes the aforesaid limitations and compared with the conventional MLI in terms of the number of switches, DC sources, capacitors, fundamental voltage, and THD. The performance is analyzed by using a simulation tool.