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Volume 5 Issue 1 September - November 2014

Article

Review On Tunnel SRAM For Low Power Applications

Alka Parihar* , VimalKumar Mishra, R. K. Chauhan*

* PG Scholar, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, UP, India.

Research Scholar, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, UP, India.

* Professor, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, UP, India.

Parihar, A., Mishra, V.K., and Chauhan, R.K. (2014). Review On Tunnel SRAM For Low Power Applications. i-manager’s Journal on Electronics Engineering, 5(1), 1-5. https://doi.org/10.26634/jele.5.1.3316

Abstract

This paper presents a brief review on different types of Tunnel Static Random Access Memory that has been proposed for low power applications. Many authors and researchers have worked on tunnel SRAM, RTD/HFET low standby power, SRAM gain, cell and Bistable Body Tunnel SRAM and demonstrated the accomplished improvements in power dissipation and performance compared with previous designs for low-power memory operation. It broadly relates to SRAM cell employing a Tunnel Switched Diode (TSD) that acts as the storage medium and is controlled by a pass transistor.

References

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[3]. J. Y.C. Sun, "CMOS Technology for 1.8V and Beyond", (1997). International Symposium on VLSI Technology, Systems and Applications, Digest of Technical Papers, pp. 293-297.

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[8]. J. P. A. van der Wagt, A. C. Seabaugh, G. Klimeck, E. A. Beam, III, T. B. Boykin, R. C. Bowen, and R. Lake (1997). “Ultralow current-density RTD's for tunneling-based SRAM,” th in Proc. 24 Int. Symp. pp. 601-604.

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[11]. V. George et al., (2007). "Penryn: 45-nm next generation Intel core 2 processor," IEEE Asian Solid-State Circuits Conference, pp.14-17.

[12]. Yih Wang et al., (2008). "A 1.1 GHz 12 µA/Mb- Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications," IEEE Journal of Solid-State Circuits, Vol.43, No.1, pp.172-179.

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[15]. K. Osada, Y. Saitoh, E. Ibe, and K. Ishibashi, (2003). “16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM for handling cosmic-ray-induced multi-errors,” IEEE Int. Solid- State Circ. Conf. (ISSCC) , pp. 302–303.

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Article

Review On SOI MOSFET For Low Power Digital Application

Nitu Rao* , VimalKumar Mishra, R. K. Chauhan*

* PG Scholar, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, UP, India.

Research Scholar, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology,UP, India.

* Professor, Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, UP, India

Rao, N., Mishra, V.K., and Chauhan, R.K. (2014). Review On SOI MOSFET For Low Power Digital Application. i-manager’s Journal on Electronics Engineering, 5(1), 6-12. https://doi.org/10.26634/jele.5.1.3317

Abstract

Several Metal Oxide Semiconductor (MOS) structures are discussed in this paper namely Silicon on Insulator (SOI) MOSFET, Partially Depleted (PD) SOI MOSFET, Fully Depleted (FD) SOI MOSFET and tunnel diode body contact MOSFET. SOI MOSFET has certain advantages over conventional bulk MOSFET in terms of reduced short channel effect and drain induced barrier lowering. But SOI MOSFET has certain problems due to its buried oxide layer. So the comparative study of different SOI MOSFET over bulk MOSFET has been taken. To overcome the problem of Floating Body Effect and high series resistance different structures of FD SOI MOSFET are explained in brief. A Tunnel Diode Body Contact SOI MOSFET is also studied in this paper to overcome the problem of Floating Body Effect in PD SOI MOSFET.

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Research Paper

Aircraft Asylum Monitoring SystemUsing SPARTAN6 FPGA

S.N. Bhuvaneshwari* , M. Elakkiyapriya, M. Shenbagapriya*

,UG Scholar, Electronics And Communication Engineering, Knowledge Institute Of Technology, Salem, India

Assistant Professor, Knowledge Institute of Technology, Electronics and Communication Engineering, Salem, India

Bhuvaneshwari, S. N., Elakkiyapriya, M., and Shenbagapriya, M. (2014). Aircraft Asylum Monitoring System Using SPARTAN6 FPGA. i-manager’s Journal on Electronics Engineering, 5(1), 13-20. https://doi.org/10.26634/jele.5.1.3318

Abstract

Aircraft provides a Fast Reliable mode of transport with no comparable alternative for long distance. This paper is used to get the information about the plane, if any accidents or hijack occurs in the plane. The jumbo level sensor used in the plane activates and gives us the digital information about the direction and distance of landing of the plane to the controller. Then the controller allows the signal from the control room to the plane. The TI OMAP in Spartan 6 FPGA used in this paper demonstrates the action in control, the braking, and nose landing gear of the plane. The magnetic sensor also activates, while the controller receives the signal, which deactivates or magnetize the weapons in the plane. This project is mainly used for the aircraft system. It has few advantages with, High safety for plane and passengers, by reducing the plane's hijack and accidents and is easy to find the plane tracking and control. It is also easy to handle the equipment. This concept has been implemented in Unified Learning Platform kit which increases the efficiency.

References

[1]. Dugan, Laura, Gary Lafree, Alex R. Piquero (2005). “Testing a rational choice model of airline hijackings” Criminology, Vol.43, No.4.

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Research Paper

Design And Implementation Of Different Digital Modulation Analysis For Optical Communications

M. Devarajan* , A. Karikalan**

* PG student, Kingston Engineering College, Vellore, India

** Assistant Professor, Department of Electrical and Electronics Engineering, Kingston Engineering College, Vellore, India.

Devarajan, M., and Karikalan, A. (2014). Design And Implementation Of Different Digital Modulation Analysis For Optical Communications. i-manager’s Journal on Electronics Engineering, 5(1), 21-26. https://doi.org/10.26634/jele.5.1.3319

Abstract

This paper, presents a method to describe all modulation techniques such as BPSK, ASK, FSK, QPSK, OOK. These are compared based on bandwidth requirement, power efficiency, transmission capacity and bit error probability. The modulators are the basic requirement of optical communication systems and they have been designed to reduce the channel distortion, and hence many types of modulation techniques have been proposed here. This paper, mainly focuses on the hardware realization of such several modulation schemes with a minimum area strategy for the universal mobile telecommunication system when it comes to power and error performance. Here MATLAB software is used for simulation and result analysis.

References

[1]. Ghafour Amouzad, Mahdiraji and Edmond Zahedi (2006). “Comparison of Selected Digital Modulation Schemes for Wireless Optical Communications”, 4th Student Conference on Research and Development (SCOReD), Malaysia, 27-28.

[2]. G. Mahesh Naidu, O. Sudhakar, V. Sailaja, (2013). “Simulation of BPSK Modulation and Demodulation on System Generator” International Journal of Scientific Engineering and Research (IJSER), Vol. 1 Issue 2.

[3]. Preksha R. Kolankar, Swati V. Sakhare, (2014). “FPGA Implementation of QPSK modulator by using Hardware Co-simulation”, International Journal of Engineering Research and Development, Vol 10, Issue 4.

[4]. Rohit Garg, Ankita Mittal, (2014). “Design & Implementation for Combination of QPSK & BPSK Modulation Technique”,International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE), Volume 3, Issue 8.

[5]. Gaurav Purohit , Divya Vyas , Kota Solomon Raju, (2013). “Hardware Co-simulation of BPSK and QPSK For Software Defined Radio”, International Journal Of Electronics and Communication Engineering & Technology, Special Issue (November), pp. 301-308.

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[8]. Molabanti Praveen Kumar, T. S. R Krishna Prasad, M . Vijaya Kumar, (2013). “Implementation of Digital Communication Laboratory on FPGA”, International Journal of Advanced Research in Computer and Communication Engineering, Vol. 2, Issue 11.

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[11]. Farhan A. Ghaffar, Atif Shamim, M. Kashan Mobeen, Tareq Y. AlNafouri, Khaled N. Salama, (2011). “A Compact QPSK Modulator with Low Amplitude and Phase Imbalance for Remote Sensing Applications”, Canadian Journal on Electrical and Electronics Engineering Vol. 2, No. 4.

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Research Paper

VLSI Design Of Low Energy Modeling For Network On Chip (NoC) Applications

Jeeva Anusha* , V. Thrimurthulu**

* M.Tech VLSI SD Student, CR Engineering College, Tirupathi, Chittoor (Dist), Andhra Pradesh, India.

** Professor, Head of ECE Department, CR Engineering College, Tirupathi, Chittoor (Dist), Andhra Pradesh, India.

Anusha, J., and Thrimurthulu, V. (2014). VLSI Design Of Low Energy Modeling For Network On Chip (NoC) Applications. i-manager’s Journal on Electronics Engineering, 5(1), 27-32. https://doi.org/10.26634/jele.5.1.3320

Abstract

As technology trends advances, workstation chips become increasingly parallel, and efficient communication substrate is decisive for meeting performance and energy targets. Also as nano technology shrinks day by day work station chips are migrated to SOIC – System On Integrated Chip, which leads to many challenges in the design era, and is more critical for communication applications such as Network on Chip (NoC) and also as technology shrinks, the power supply of NoC links starts to struggle with that of NoC routers. In this paper, the authors propose the use of efficient data encoding techniques as a practical way to reduce both power dissipation and energy consumption of NoC links. In this work, the authors target the core cause of network energy consumption through techniques that reduce link and router-level switching commotion. The proposed encoding techniques are simulated and verified by Xilinx tools along with Virtex – 5 FPGA board.

References

[1]. Nima Jafarzadeh, Maurizio Palesi, Member, IEEE, Ahmad Khademzadeh, and Ali Afzali-Kusha, (2013). Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip, IEEE Transactions on VLSI System, Vol. 22, No. 3, pp.675-685.

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Research Paper

CPW-FED Dual Band Notched Fractal PatchAntenna For UWB Applications

B. Divya Gayathri* , S. Thulasi prasad**

* M.Tech, Communication Systems, Sree Vidyanikethan Engineering College, Tirupathi

** Associate Professor, Sree Vidyanikethan Engineering College, Tirupathi

Gayathri, B.D., and Prasad, S.T. (2014). CPW-FED Dual Band Notched Fractal Patch Antenna For UWB Applications. i-manager’s Journal on Electronics Engineering, 5(1), 33-38. https://doi.org/10.26634/jele.5.1.3321

Abstract

Modern communication systems put demand on antennas which operate over multiple range of frequencies, within shrunken size, less weight and high gain. For wireless applications like wireless home networking, wireless USB, Ultra Wide Band (UWB) antenna plays an important role. For achieving UWB performance, a Coplanar Waveguide (CPW) fed fractal tree patch antenna is proposed. As UWB operates under a wide range of frequency band, for achieving band rejection function, a Folded T-Shaped Element (FTSE) is embedded in the radiating patch. The notch band is 3.3-4.2GHz. Simulation results shown that the antenna exhibits preferred VSWR levels in the entire impedance bandwidth. Pair of rectangular notches are included in the ground plane for extending the antenna's impedance bandwidth. The results show that the antenna covers the frequency range from 3.1-11.1 GHz with VSWR ≤ 2. Dimensions of antenna is 14 × 18 × 1mm³ .

References

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[3]. J.Anguera, J.P.Daniel, C.Borja, J.Munbru, C.Puente, T.Leduc, N.Laeveren and P.Van Roy, (2008). “Metallized foams for fractal-shaped microstrip antennas', IEEE Antennas Propag. Mag., Vol.50, No.6, pp. 20-38.

[4]. J.Anguera, E.Martinez, C.Puente, and E.Rozan, (2003). ”The fractal Hilbert monopole: A two dimensional wire”, Microw. Opt. Technol. Lett. Vol.36, No.2, pp. 102- 104.

[5]. M.N. Jahromi, A.Falahati, and R.M.Edwards, (2011). “Bandwidth and impedance matching enhancement of fractal monopole antennas using compmct grounded coplanar waveguide,” IEEE Trans. Antennas Propag., Vol. 59, No. 7, pp.2480-2487.

[6]. B.Ozbakis and A.Kustepeli, (2008). “The resonant behavior of the Fibonacci fractal tree antennas, “Microw. Opt. Technol. Lett.,Vol. 50, No. 4, pp.1046-1050.

[7]. H.Oraizi and S.Hedayati, (2011). “Miniaturized UWB monopole microstrip antenna design by combination of Giusepe Peano and Sierpinski carpet fractals,” IEEE Antennas Wireless Propag. Lett, Vol. 10, pp. 172-175.

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[9]. M.Naser_Moghdasi, R.A.Sadeghzadeh, and B.S.Virdee, (2010). “CPW-fed compact slot antenna for WLAN operation in a laptop computer,” Microw. Opt. Technol. Lett., Vol. 52, pp. 870-873.

[10]. C.Deng, Y.J.Xie and P.LI, (2009). “CPW-fed planar printed monopole antenna with impedance bandwidth enhanced,” IEEE Antennas Wireless Propag. Lett., Vol. 8, pp. 1394-1397.

[11]. C.C.Lin, P.Jin, and R.W.Ziolkowski, (2012). “Single, Dual and tri-band-notched ultra wideband (UWB) antennas using capacitively loaded loop (CLL) resonators,” IEEE Trans. Antennas Propag., Vol. 60, No.1, pp. 102-109.

[12]. N.Ojaroudi and M.Ojaroudi, (2012). “Dual Band- Notch square monopole antenna with a modified ground plane for UWB applications,” Microw. Opt.Technol. Lett., Vol. 54, No. 12, pp.2743-2747.

[13]. K.S.Ryu and A.A Kishk, (2009). “UWB antenna with single or dual band-notches for lower WLAN band and upper WLAN band,” IEEE Trans. Antenna Propag., Vol.57, No. 12,pp.3942-3950.

[14]. M.Ojaroudi, G.Ghanbari, N.Ojaroudi, and C.Ghobadi, (2009). “Small square monopole antenna for UWB applications with variable frequency band-notch function”, IEEE Antennas Wireless Propag. Lett., Vol. 8, pp. 1061-1064.

[15]. R.Zaker, C.Ghobadi, and J.Nourinia, (2009). “Band width enhancement of novel compact single and dual band- notches printed monopole antenna with a pair of LShaped slots”, IEEE Trans. Antennas Propag., Vol. 57, No.12, pp. 3978-3983

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i-manager's Journal on Electronics Engineering (JELE)

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CPW-FED Dual Band Notched Fractal PatchAntenna For UWB Applications

B. Divya Gayathri* , S. Thulasi prasad**

* M.Tech, Communication Systems, Sree Vidyanikethan Engineering College, Tirupathi ** Associate Professor, Sree Vidyanikethan Engineering College, Tirupathi

Gayathri, B.D., and Prasad, S.T. (2014). CPW-FED Dual Band Notched Fractal Patch Antenna For UWB Applications. i-manager’s Journal on Electronics Engineering, 5(1), 33-38. https://doi.org/10.26634/jele.5.1.3321

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Alka Parihar* , VimalKumar Mishra, R. K. Chauhan*

Nitu Rao* , VimalKumar Mishra, R. K. Chauhan*

S.N. Bhuvaneshwari* , M. Elakkiyapriya, M. Shenbagapriya*

,UG Scholar, Electronics And Communication Engineering, Knowledge Institute Of Technology, Salem, India

Assistant Professor, Knowledge Institute of Technology, Electronics and Communication Engineering, Salem, India

* PG student, Kingston Engineering College, Vellore, India

** Assistant Professor, Department of Electrical and Electronics Engineering, Kingston Engineering College, Vellore, India.

* M.Tech VLSI SD Student, CR Engineering College, Tirupathi, Chittoor (Dist), Andhra Pradesh, India.

** Professor, Head of ECE Department, CR Engineering College, Tirupathi, Chittoor (Dist), Andhra Pradesh, India.

* M.Tech, Communication Systems, Sree Vidyanikethan Engineering College, Tirupathi

** Associate Professor, Sree Vidyanikethan Engineering College, Tirupathi