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i-manager's Journal on Electronics Engineering (JELE)

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An Intelligent Base Link Recovery Management and Path Stability in Clustered Randomly Distributed Mobile Ad Hoc Networks
A High-Performance Dual Classifier Based Packet Classification Engine on FPGA
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Volume 4 Issue 4 June - August 2014

Article

I/O Average And Maximum CurrentConsumption Calculation

Andrey Malkov* , Lin Wang, Evgeny Shevchenko*

* I/O Design Group, Freescale Semiconductor, Moscow, Russia.

Hardware Application Team, Freescale Semiconductor, Shanghai, China.

* Manager, I/O Design Team, Freescale Semiconductor, Moscow, Russia.

Malkov, A., Wang, L., and Shevchenko, E. (2014). I/O Average And Maximum Current Consumption Calculation. i-manager’s Journal on Electronics Engineering, 4(4), 1-4. https://doi.org/10.26634/jele.4.4.3194

Abstract

Power Integrity (PI) is becoming increasingly important in today's high-speed digital I/O interfaces. Power integrity for I/O interfaces is related to the voltage variations in the power/ground network due to the noise. The power/ground noise causes various problems in high-speed systems, such as logic failure, EMI, timing delay, and jitter. For the Power Integrity analysis of the I/O padring of the chip, it is very important to quickly calculate I/O current consumption at the early stage of the project, without running extensive time-consuming spice simulations of entire I/O bank. PI analysis needs both I/O padring and PCBdata, and simulation tool considers them simultaneously [5],[6],[7],[10]. Two useful formulas are given in this article and explained below that can easily allow to estimate average and maximum IO current consumption, using example of i.MX6 series applications processors of Freescale Semiconductor, Inc. Resulting numbers correlate well with real I/O circuit spice simulation data.

References

[1]. Henry W. Ott, (2009). “Electromagnetic Compatibility Engineering”, ISBN 978-0-470-18930-6pp. 428.

[2]. Lee W. Ritchey, “Right The First Time - A Practical Handbook on High-Speed PCB and System Design”, pp. 353.

[3]. Freescale Semiconductor i.MX6 series applications processors Datasheet at http://www.freescale.com/ webapp/sps/site/prod_summary.jsp?code=i.MX6Q&fps p=1&tab=Documentation_Tab

[4]. Vishram S. Pandit, Woong Hwan Ryu, Myoung Joon Choi, “Power Integrity for I/O Interfaces: With Signal Integrity/ Power Integrity Co-Design (Prentice Hall Signal Integrity Library)”, ISSBN -13: 970-0-137-01119-3, pp. 1- 383.

[5]. M. Swaminathan, E. Engin, “Power Integrity Modeling and Design for Semiconductors and Systems”, Prentice Hall, press.

[6]. M.J. Choi, and V. Pandit, (2009). “SI/PI Co-Analysis for I/O Interfaces,” IBIS Summit.

[7]. Eric Bogatin, (2009). “Signal and Power Integrity – Simplified2nd Edition”, Hardback.

[8]. Masanori Hashimoto & Raj Nair, (2011). “Power Integrity for Nanoscale Integrated Systems”, A practical handbook for designing with power supply noise.

[9]. Vishram S. Pandit and others, (2009). “SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity”, DESIGNCON.

[10]. I. Novak (2008). (Executive Editor), “Power Distribution Design Methodologies” IEC, ISBN: 978-1-931695-65-7.

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Research Paper

Improvement In Noise Figure Using CMOSBroadband Sub-Threshold Mixer

Nimain Charan Nayak*

Professor, MNM Jain Engineering College, Chennai, India.

Nayak, N.C. (2014). Improvement In Noise Figure Using CMOS Broadband Sub-Threshold Mixer. i-manager’s Journal on Electronics Engineering, 4(4), 5-10. https://doi.org/10.26634/jele.4.4.3195

Abstract

This paper presents a broadband low noise mixer based on a double balanced Gilbert cell that works between 1-6 GHz. One of the most important factors of the mixer noise figure is flicker noise. All transistors in this design are biased in the subthreshold region in order to suppress mixer noise figure. Also dynamic current injection circuit (current bleeding circuit) has been utilized to improve the noise performance. Shunt peaking technique is adopted to have a flat conversion gain. The simulation results of the designed mixer show 21.1 dB conversion gain and 6.41 dB average noise figure at 1 GHz - 6 GHz. Also simulation results demonstrate that, using current bleeding circuit, low noise figure is obtained . Its consumption power is 10.6 mW at 1.8V supply voltage. The noise figure is an important parameter to be considered in the design of Gilbert cell mixer and is further improved using the proposed method. A dynamic current injection technique with a tuning inductor has been employed in the mixer design in order to reduce the output noise corner frequency. The traditional Gilbert based wideband active mixers realized by pure bipolar and MOSFET have been demonstrated in recent years.

References

[1]. K. Chen, and S. Liu, (2012). “Inductor less Wideband CMOS Low-Noise Amplifiers Using Noise-Canceling Technique,” IEEE Transactions on Circuits and Systems— I, pp. 1-10.

[2]. Y. Hwang, S. Wang, S. Yan, and J. Chen, (2010). “An inductor less wideband noise-cancelling CMOS low noise amplifier with variable-gain technique for DTV tuner application,” Int. J. Electron. Commun, pp.1009-1014.

[3]. S. S. K. Ho, and C. E. Saavedra, (2010). “A CMOS Broadband Low-Noise Mixer with Noise Cancellation,” IEEE Transactions on Microwave Theory and Techniques, pp. 1126-1132.

[4]. Z. Cheng, P. Zhou, J. Li, and S. Zhang, (2010). “An Improved Current Bleeding Mixer based on CMOS technology, ”International Conference on Communications and Mobile Computing, pp. 128-131.

[5]. H. Darabi, and J. Chiu, (2005). “A Noise Cancellation Technique in Active RF-CMOS Mixers,” IEEE Journal of Solid-State Circuits, pp. 2628-2632.

[6]. K. Y. Tong, B. K. Ma, and H. T. Yuen, (2004). “Thermal noise in RF CMOS mixers,” Solid-State Electronics, pp. 759–763.

[7]. J. Yoon, H. Kim, C. Park, J. Yang, H. Song, S. Lee, and B. Kim, (2008). “A New RF CMOS Gilbert Mixer With Improved Noise Figure and Linearity,” IEEE Transactions on Microwave Theory and Techniques, pp. 626-631.

[8]. L. A. MacEachern, and T.Manku, (1998). “A chargeinjection method for Gilbert cell biasing, “IEEE Canadian Conference, pp. 365-368.

[9]. J. Park, C. Lee, B. Kim, and J. Laskar, (2006). “A Low Flicker Noise CMOS Mixer Using Two Resonating Inductors for Direct Conversion Receivers,” Microwave Symposium Digest, pp. 1705-1708.

[10]. J. Bae. Seo, K. M. Park, J. Ha. Kim, J. H. Park, Y. S. Lee, J. H. Ham, and T. Y. Yun, (2007). “A Low-Noise UWB CMOS Mixer Using Switched Biasing Technique,” International Workshop on Radio-Frequency Integration Technology, pp. 42-45.

[11]. A. I. A. Galal, M. A. Abdelghany, R. K. Pokharel, H. Kanaya, and K. Yoshida, (2010). “A Low Power Low Flicker Noise Merged Balun LNA and Mixer for 5.2GHz Wireless LAN Receivers,” TENCON 2010, pp. 1517-1520.

[12]. S. R. Feng, L. Huailin, Y. Tao, H. Ru, and W. Y. Yuan, (2006). “Design of a 3-5GHz BiFET mixer for ultra wideband application,” ICSICT, pp. 1538 – 1540.

[13]. M. Jouri, A. Golmakani, M. Yahyabadi, and H. Khosrowjerdi, (2010). “Design and Simulation of a downconversion CMOS mixer for UWB applications,” ECTI-CON, pp. 937 – 940.

[14]. Y. Gao, F. Huang, J. Cheng, and L. Wu, (2009). “A 3.1- -4.8 GHZ Wideband Mixer for MB-OFDM UWB Receivers With Improved Noise Per formance,” IEEE Youth Conference on Information, Computing and Telecommunication, pp. 5-61.

[15]. H. Elyasi, and A. Nabavi, (2011). “Design of a Kuband Gilbert Mixer with Gain, Noise Figure and Linearity Enhancement,” ICEE, pp. 1-6.

[16]. M. A. Abdelghany, R. K. Pokharel, H. Kanaya, and K. Yoshida, (2011). “A low flicker noise direct conversion receiver for IEEE 802.11g wireless LAN using differential active inductor,” Microelectronics Journal, pp. 283–290.

[17]. S. K. Hampel, O. Schmitz, M. Tiebout, and I. Rolfes, (2010). “Inductor less Low-Voltage and Low-Power Wideband Mixer for Multistandard Receivers,” IEEE Transactions On Microwave Theory And Techniques, pp. 1384-1390.

[18]. J. Park, C. Lee, B. Kim, and J. Laskar, (2006). “Design and Analysis of Low Flicker-Noise CMOS Mixers for Direct- Conversion Receivers,” IEEE Transactions on Microwave Theory and Techniques, pp. 4372-4380.

[19]. D. Ful, L. Huang, H. Du, and H. Yuanl, (2008). “A O.18µm CMOS High Linearity Flat Conversion Gain Downconversion Mixer for UWB Receiver,” ICSICT, pp. 1492 – 1495.

[20]. R. M. Weng, M. J. Zeng, and C. Y. Liu, (2011). “A High Gain Flatness High Linearity Down Conversion Mixer for Ku Band Application,” ISCAS, pp. 2749 – 2752.

[21]. W. Elgharbawy, p. Golconda, A. Kumar, and M. Bayoumi, (2005). “A New Gate-Level Body Biasing Technique For PMOS Transistors In Sub threshold CMOS Circuits,” ISCAS, pp. 4697 – 4700.

[22]. A. C. Heiberg, T. W. Brown, T. S. Fiez, and K. Mayaram, (2011). “A 250 mV, 352 µW GPS Receiver RF Front-End in 130 nm CMOS,” IEEE Journal of Solid-State Circuits, pp. 938-949.

[23]. M. M. Reja, K. Kambiz, and I. Filanovsky, (2008). “A Novel 0.6V CMOS Folded Gilbert-Cell Mixer for UWB Application,” in proc. IEEE International Conference on SOC, pp.169–172.

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Research Paper

Flip Flop Based Multilevel Inverter TopologyUsing Digital Control

C. R. Balamurugan* , S. P. Natarajan, M. Arumugam*, R. Bensraj****

Balamurugan, C.R., Natarajan, S.P., Arumugam, M., and Bensraj, R. (2014). Flip Flop Based Multilevel Inverter Topology Using Digital Control. i-manager’s Journal on Electronics Engineering, 4(4), 11-14. https://doi.org/10.26634/jele.4.4.3196

Abstract

Multilevel inverter is a device which is capable of producing different voltage levels. The proposed multilevel inverter has been analyzed in both symmetric and asymmetric operation modes.This paper proposes cascaded multilevel inverter using flip flop and logic gate. By using the four bit counter, the Boolean equation is formed from the switching table. The equations are given as the input to each switch of the multilevel inverter by using the logic gates. The proposed topologies can produce the outputs which are nearer to the sinusoidal wave. This proposed system is used to reduce the Total Harmonic Distortion (THD). A great perfection in voltage level number with minimum switching devices has been obtained in both symmetric and asymmetric modes. Thereafter a detailed study of losses and Peak Inverse Voltage (PIV) of the proposed multilevel inverter is given.Finally a computer simulation using Matlab/Simulink is presented and a laboratory prototype implementation verifies the results.

References

[1]. Kang D.W,Hyun, D.S. (2010). “Simple Harmonic Analysis Method For Multi-Carrier PWM Techniques using Output Phase Voltage In Multilevel inverter”, Electric Power Applications IEE Proceedings, Vol.152, pp.157- 165

[2]. Boora, A.A.,Nami, A. Zare, F., Ghosh, A., Blaabjerg, F. (2010).” Voltage-sharing converter to supply single-phase asymmetrical four-level diode-clamped inverter with high power factor loads”, IEEE Transaction on Power Electronics, Vol. 25 , pp. 2507 - 2520.

[3]. Nami.A, Zare, F, Ghosh,A, Blaabjerg, F., (2011). “A Hybrid Cascaded converte topology with series connected symmetrical and Asymmetrical Diode-Clamped H-Bridge cells”, IEEE Trans. Power Electron., Vol. 26, No. 1, pp. 51-65.

[4]. Pereda, J. Dixon, J, (2011). “High-Frequency Link: A Solution for Using Only One DC Source in Asymmetric Cascaded Multilevel Inverters”, IEEE Transactions on Industrial Electronics, Vol. 58 , pp. 3884 - 3892.

[5]. Najafi, E. ,Yatim, A.H.M., (2012). ”Design and Implementation of new Multilevel Inverter Topology”, IEEE Transactions on Industrial Electronics, Vol. 59, pp. 4148-4154.

[6]. Kangarlu,M.F. , Babaei,E. , Laali,. (2012). “Symmetric multilevel inverter with reduced components based on non- insulated dc voltage sources”, IET Power Electronics, Vol. 5 , pp. 571 – 581.

[7]. Al-Judi, A. ,and Nowicki, E. (2012). “Cascading of diode bypassed transistor-voltage-source units in multilevel inverters”, IET Power Electronics, Vol.6, pp.554 - 564

[8]. Kangarlu,M.F,. and Babaei, E, (2013). “A Generalized Cascaded Multilevel Inverter Using Series Connection of Sub multilevel Inverters”, IEEE Transactions on Power Electronics, Vol. 28, pp. 625 - 636,

[9]. Babaei, E. , Alilu, and S.,,Laali, S., (2014). ”A New General Topology for Cascaded Multilevel Inverters With Reduced Number of Components Based on Developed H-Bridge”, IEEE Transactions on Industrial Electronics, Vol. 61, pp.3932 – 3939,

[10]. Palanivel, P. , and Dash, S.S. (2014). “Analysis of THD and output voltage performance for cascaded multilevel inverter using carrier pulse width modulation techniques”, IET Power Electronics, Vol.4,pp.951-958.

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Research Paper

Design Of Electronic Circuits Using ParallelGenetic Algorithms

Mohammed A. Abdala* , Ali Usam AlCherchefchi**

* Associate Professor, College of Information Engineering, Nahrain University, Baghdad, Iraq.

** College Information Engineering, Nahrain University, Baghdad, Iraq.

Abdala, M.A., and Usamalcherchefchi, A. (2014). Design Of Electronic Circuits Using Parallel Genetic Algorithms. i-manager’s Journal on Electronics Engineering, 4(4), 15-20. https://doi.org/10.26634/jele.4.4.3197

Abstract

An electronic circuit design based on Parallel Genetic Algorithm (PGA) is presented in this paper. The design uses SPICE Simulation Program with Integrated Circuit Emphasis to evaluate the circuit performance and compare it to the requirements. A Parallel Genetic Algorithm is designed and implemented on a group of desktop PCs running Windows XP nd and connected together using a standard Ethernet office network. The PGA is used in the design of several circuits, 2^nd order active Low Pass Filters, a 6^th order active LPF, (Low Pass Filter) and a CMOS (Complementary Metal Oxide Semiconductor) operational amplifier. The result shows the excellent extraction of circuit performance characteristics from the SPICE for different circuit types and also the importance of the algorithm increases as the complexity of the circuit increases. The parallelization achieved a speedup of about (19) times faster than a sequential implementation by using (20) processors. Further speedup is expected if more processors are used. The system is implemented using the C++ programming language.

References

[1]. Dr. Thomas Back. (1996). “Evolutionary Algorithms in Theory and Practice”. Oxford University Press. ISBN 0-19- 509971-0.

[2]. Erick Cantú-Paz. (1998). “A Survey of Parallel Genetic Algorithms”. Calculateurs Parallèles, réseaux et systèmes répartis. Vol 10, No. 2, pp 141-171.

[3]. Erick Cantu-Paz. (2001). “Efficient and Accurate Parallel Genetic Algorithms”. Kluwer Academic Publishers.

[4]. Lance Chambers. (2001). “The Practical Handbook of Genetic Algorithms: Complex Coding Systems”, Volume 3. Chapman & Hall/CRC.

[5]. Kenneth V. Noren, John E. Ross. (2001). “Analog Circuit Design Using Genetic Algorithms”. OSEE.

[6]. David A. Coley. (1999). “An Introduction to Genetic Algorithms for Scientists and Engineers”. World Scientific Publishing Co. Pte. Ltd., pp. 1-211.

[7]. Ricardo Salem Zebulum, Marco Aurélio Pacheco, Marley Maria B.R. Vellasco. (2001). “Evolutionary Electronics - Automatic Design of Electronic Circuits and Systems by Genetic Algorithms”. CRC Press.

[8]. S . N . S i v a n a n d a m a n d S . N . D e e p a . ( 2 0 0 8 ) . “Introduction to Genetic Algorithms”. Springer. ISBN 978- 3-540-73190-0

[9]. Jason D.Lohn, Silvano P. Colombano, Gary L. Haithy, Dimitris Stassinopoulos. (2006). “A Parallel Genetic Algorithm for Automated Electronic Circuit Design”. Computational Sciences Division, Recom Technologies, Inc., NASA Ames Research Center.

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Research Paper

A Novel Based Approach For A HighSpeed 24 Bit Multiplier

Duvvuru Praveen Kumar* , M. Bharathi, Tounga Mounika*

, M.Tech Student, VLSI, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College (Autonomous), Tirupathi, Andhra Pradesh, India.

Assistant Professor, Department of Electronics and Communication Engineering, Sree Vidyanikethan Engineering College (Autonomous), Tirupathi, Andhra Pradesh, India.

Kumar, D.P., Bharathi, M., and Tunga, M. (2014). A Novel Based Approach For A High Speed 24 Bit Multiplier. i-manager’s Journal on Electronics Engineering, 4(4), 21-24. https://doi.org/10.26634/jele.4.4.3198

Abstract

Multiplication plays an important role in most mathematical applications. Among the four arithmetic operations, multiplier is the most important one. In this paper, the authors have proposed a multiplier which operates on two 24 bit of digital numbers, which is a 24 bit multiplier. In order to construct a 24 bit multiplier, the authors used Dadda reduction technique. Dadda reduction technique operates on two 24 bit numbers , hence called a 24 bit multiplier. These higher bit multipliers are used in floating point multiplications, i.e., floating point operates based on single precision and double precision numbers. In order to operate them while doing multiplication, the mantissa has 24 bits, whereas double precision requires 48 bits. This is designed using Verilog Hardware description language. This is simulated using Xilinix ISE 10.1 and being implemented on Spartran 3E of FPGA.

References

[1]. Jeeven B, Narendra S, Dr.C.V.Krishna Reddy and Dr. K. Sivani (2013), “A High Speed Floating Point Multiplier using Dadda Algorithm”, IEEE, IBSN: 978-1-4673-5089-1,pp. 455-460.

[2]. Laxman S, Darshan Prabhu R, Mahesh S Shetty ,Mrs. Manjula BM, Dr. Chirag Sharma, (2012). “FPGA implementation of different Multiplier Architectures”, IJETAE, ISSN: 2250-2459, Vol. 2, No.6, pp. 292-295.

[3]. Jan M.Rabaey, A.P. Chandrakasan and B. Nikolic (2003). “Digital Integrated Circuits, A Design Perspective”, nd 2 ed., Prentice hall electronics and VLSI series, Pearson Education.

[4]. Navabi (2008), “Verilog Digital System Design” Mc Graw Education, ISBN: 9780070252219, pp.1-400.

[5]. Thomas & Moorbys (2001), “Verilog Hardware Description Language”, Fifth Edition, Kluwer Academic Publishers, ISBN: 9780306476662, pp. 1-404..

[6]. www.wikipedia.com

[7]. “Design and implementation of Floating Point multiplier using Wallace and Dadda Algorithm”, http://www.irjece.com/Downloads/vol1/issue1/08.1RJECE 10085.pdf.

[8]. Madhu Thakur and Javed Ashraf (2012), “Design of Braun Multiplier with Kogge Stone Adder & Its Implementation on FPGA”, International Journal of Scientific & Engineering Research, ISSN: 2229-5518, Vol. 3, No. 10, pp. 03-06.

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Research Paper

Comparative Analysis Of Integrated Wideband/NarrowBand Antenna For Cognitive Radio Applications

Srither A* , E. D. Kanmani Ruby**

* PG Student, Department of Electronics and Communication Engineering, School of Communication and Computer Sciences, Kongu Engineering College, India.

** Professor, Department of Electronics and Communication Engineering, School of Communication and Computer Sciences, Kongu Engineering College, India

Srithar, A., and Ruby, E.D.K. (2014). Comparative Analysis Of Integrated Wideband/Narrow Band Antenna For Cognitive Radio Applications. i-manager’s Journal on Electronics Engineering, 4(4), 25-36. https://doi.org/10.26634/jele.4.4.3199

Abstract

Cognitive radio is an inventive system to wireless technologies, in which radios are designed with an astonishing level of intelligence and agility. This handles the available spectrum in an expedient manner to avoid spectrum scarcity. The cognitive radio antenna consists of integrated wideband and narrow band antenna in same substrate which is taxing task. A UWB (Ultra Wide Band) antenna is pondered for the wide band operation which has the bandwidth of 7.5GHz respectively used for sensing vacant slots in the spectrum. Narrow band antenna and pattern Reconfigurable antenna are usually used for transmission of data through the vacant slots from the outcomes of sensing antenna. In this paper, the various cognitive radio antennas are investigated in tremendously.

References

[1]. Federal Communications Commission, (2002). “Revision of part 15 of the Commission's Rules Regarding Ultra-Wideband Transmission Systems,” Tech. Rep. ETDocket 98-153, FCC02-48,

[2]. Simon Haykin, Life fellow, (2005). “Cognitive Radio: Brain-Empowered Wireless Communications”, IEEE Journal on selected areas in communications, Vol. 23, No.2.

[3]. I. Akyildiz, W. Lee, M. Vuran, and S. Mohanty, (2006). “Next generation/dynamic spectrum access/cognitive radio wireless networks: a survey”, Computer Networks, Vol. 50, No. 13, pp. 2127–2159.

[4]. Q. Zhao and B. M. Sadler, (2007). “A Survey of Dynamic Spectrum Access,” IEEE Signal Processing Magazine, Vol. 24, No. 3, pp. 79–89.

[5]. J. Wang, M. Ghosh, and K. Challapali, (2011). “Emerging Cognitive Radio Applications: A Survey”, IEEE Communications Magazine, Vol. 49, No. 3, pp. 74–81.

[6]. Aboufoul T , Ali K, Alomainy A, Parini C, (2013). “Combined pattern and frequency reconfiguration of single-element ultra-wideband monopole antenna for th Cognitive Radio devices” 7 European Conference on Antennas and Propagation (EuCAP), pp(s):932 – 936, EISBN :978-88-907018-1-8.

[7]. Costantine J, Tawk.Woodland, J.Flaum, N. ; Christodoulou, C.G., (2014). “Reconfigurable antenna system with a movable ground plane for cognitive radio”, Microwaves, Antennas & Propagation, IET ,Vol 8, Issue: 11, pp (s):858 – 863, ISSN: 1751-8725, DOI:10.1049/ietmap. 2013.0605.

[8]. Tawk, Y. ; Ayoub, F. ; Christodoulou, C.G. ; Costantine, J (2013). “A MIMO cognitive radio antenna system”, IEEE Antennas and Propagation Society International Symposium (APSURSI), pp (s): 572 - 573, ISSN : 1522-3965, Print ISBN: 978-1-4673-5315-1.

[9]. Mansoul, A. , Ghanem, F. , (2013). “Frequency and bandwidth reconfigurable monopole antenna for cognitive radios”, IEEE Antennas and Propagation Society International Symposium (APSURSI), pp (s): 680 – 681, ISSN: 1522-3965 Print ISBN: 978-1-4673-5315-1, DOI.

[10]. Aboufoul, T., (2014). “Polarisation reconfigurable ultra wideband antenna for cognitive radio devices”, IEEE Antennas and Propagation Society International Symposium (APSURSI), pp (s):1636 - 1637 ISSN :1522-3965 Print ISBN :978-1-4673 - 5315-1, DOI : 10.1109/APS.2013.6711477.

[11]. Narlawar, M.S. , Badjate, S.L. , (2014). “Evolution of Ultra Wide-Band Swastik Shaped Monopole Antenna for Cognitive Radio Applications”, International Conference on Electronic Systems, Signal Processing and Computing Technologies (ICESC), pp (s):79 - 83 DOI.

[12]. Mansoul, A , Ghanem, F. ; Hamid, M.R. ; Trabelsi, M. , (2014). “A Selective Frequency-Reconfigurable Antenna for Cognitive Radio Applications”, IEEE Antennas and Wireless Propagation Letters, Vol 13 pp (s): 515 - 518 ISSN : 1536-1225 ,DOI: 10.1109/LAWP.2014.2311114

[13]. Augustin, G., Chacko, B.P.; Denidni, T.A., (2014). “Electronically reconfigurable uni-planar antenna for cognitive radio applications”, Microwaves, Antennas & Propagation, IET Vol, 8 , Issue: 5 , pp. 367-376 ISSN : 1751- 8725 ,DOI: 10.1049/iet-map.2013.0287.

[14]. Pahadsingh, S. ; Sahu, S., (2014). “IntegratedCPW - fedUWB/dualnarrowbandantenna for Cognitive Radioapplication”, IEEE Signal Propagation and Computer Technology (ICSPCT), Page(s): 236 - 238 , DOI.

[15]. Rodrigues, E.J.B. ; Lins, H.W.C. ; D'Assuncao, A.G. (2014). ,“Reconfigurable Circular Ring Patch Antenna for UWB and Cognitive Radio Applications”, IEEE Antennas and Propagation (EuCAP), Page(s): 2744 - 2748 , DOI.

[16]. Augustin, G, (2014). “Diversity Antenna with Electronically Switchable Wide / Narrow band for Cognitive Radio Systems”, IEEE Antennas and Propagation( E u C A P ) , p p .3243 –3245 , DOI : 10.1109/EuCAP.2014.6902520.

[17]. Bitchikh, M., (2014). “A three-resolution UWB frequency reconfigurable Antipodal Vivaldi antenna for Cognitive Radios”, IEEE Antennas and Propagation ( EuCAP ) , p p. 3665 – 3668,DOI:10.1109/EuCAP. 2014.6902625.

[18]. Shou-Hui Zheng ; Xiong-Ying Liu ; Tentzeris, M.M. , (2014). “A Novel Optically Controlled Reconfigurable Antenna for Cognitive Radio Systems”, Antennas and Propagation Society, p p .1246-1247 , DOI : 10.1109/APS.2014.6904950.

[19]. Lei Ge ; Kwai Man Luk (2014).,“Unidirectional Antenna for Cognitive Radio Applications”, IEEE Electromagnetics (iWEM), pp (s): 14 – 15, DOI: 10.1109/iWEM.2014.6963612.

i-manager's Journal on Electronics Engineering (JELE)

Current Issue Vol. 14 Issue 1

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Volume 4 Issue 4 June - August 2014

I/O Average And Maximum CurrentConsumption Calculation

Andrey Malkov* , Lin Wang**, Evgeny Shevchenko***

* I/O Design Group, Freescale Semiconductor, Moscow, Russia. ** Hardware Application Team, Freescale Semiconductor, Shanghai, China. *** Manager, I/O Design Team, Freescale Semiconductor, Moscow, Russia.

Malkov, A., Wang, L., and Shevchenko, E. (2014). I/O Average And Maximum Current Consumption Calculation. i-manager’s Journal on Electronics Engineering, 4(4), 1-4. https://doi.org/10.26634/jele.4.4.3194

Abstract

References

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Improvement In Noise Figure Using CMOSBroadband Sub-Threshold Mixer

Nimain Charan Nayak*

Professor, MNM Jain Engineering College, Chennai, India.

Nayak, N.C. (2014). Improvement In Noise Figure Using CMOS Broadband Sub-Threshold Mixer. i-manager’s Journal on Electronics Engineering, 4(4), 5-10. https://doi.org/10.26634/jele.4.4.3195

Abstract

References

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Flip Flop Based Multilevel Inverter TopologyUsing Digital Control

C. R. Balamurugan* , S. P. Natarajan**, M. Arumugam***, R. Bensraj****

Balamurugan, C.R., Natarajan, S.P., Arumugam, M., and Bensraj, R. (2014). Flip Flop Based Multilevel Inverter Topology Using Digital Control. i-manager’s Journal on Electronics Engineering, 4(4), 11-14. https://doi.org/10.26634/jele.4.4.3196

Abstract

References

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Design Of Electronic Circuits Using ParallelGenetic Algorithms

Mohammed A. Abdala* , Ali Usam AlCherchefchi**

* Associate Professor, College of Information Engineering, Nahrain University, Baghdad, Iraq. ** College Information Engineering, Nahrain University, Baghdad, Iraq.

Abdala, M.A., and Usamalcherchefchi, A. (2014). Design Of Electronic Circuits Using Parallel Genetic Algorithms. i-manager’s Journal on Electronics Engineering, 4(4), 15-20. https://doi.org/10.26634/jele.4.4.3197

Abstract

References

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A Novel Based Approach For A HighSpeed 24 Bit Multiplier

Duvvuru Praveen Kumar* , M. Bharathi**, Tounga Mounika***

Kumar, D.P., Bharathi, M., and Tunga, M. (2014). A Novel Based Approach For A High Speed 24 Bit Multiplier. i-manager’s Journal on Electronics Engineering, 4(4), 21-24. https://doi.org/10.26634/jele.4.4.3198

Abstract

References

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Comparative Analysis Of Integrated Wideband/NarrowBand Antenna For Cognitive Radio Applications

Srither A* , E. D. Kanmani Ruby**

Srithar, A., and Ruby, E.D.K. (2014). Comparative Analysis Of Integrated Wideband/Narrow Band Antenna For Cognitive Radio Applications. i-manager’s Journal on Electronics Engineering, 4(4), 25-36. https://doi.org/10.26634/jele.4.4.3199

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Andrey Malkov* , Lin Wang, Evgeny Shevchenko*

* I/O Design Group, Freescale Semiconductor, Moscow, Russia.

Hardware Application Team, Freescale Semiconductor, Shanghai, China.

* Manager, I/O Design Team, Freescale Semiconductor, Moscow, Russia.

C. R. Balamurugan* , S. P. Natarajan, M. Arumugam*, R. Bensraj****

* Associate Professor, College of Information Engineering, Nahrain University, Baghdad, Iraq.

** College Information Engineering, Nahrain University, Baghdad, Iraq.

Duvvuru Praveen Kumar* , M. Bharathi, Tounga Mounika*