JWCN_V2_N4_RP3 P. Ratna Kamala R.V.S. Satyanarayana Journal On Wireless Communication Networks 2320 - 2351 2 4 27 32 Galios Field, RS (Reed Solomon Code), FPGA (Field Programable Gate Array) , Verilog, Error Correction & Detection The demands of achieving data integrity during transmission through coding over a wireless network have continued over time due to the high volume of data exchanged. This paper proposes an implementation of Reed Solomon code which is one of the Linear block codes that has been found to be optimal for reliable data transmission with its optimum parameters as n=255 and K=223. This optimum Reed Solomon encoder /decoder, RS(255,223) is implemented with Verilog description for Encoder and VHDL description for Decoder. This paper emphasizes on FPGA (Field Programable Gate Array) prototyping of the RS (255,223) encoder with less utilization of Hardware resources. January - March 2014 Copyright © 2014 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=2650