JSE_V3_N2_A1 Nasser Halasa Karim Al-Jebory Journal on Software Engineering 2230 – 7168 3 2 1 5 Algorithmic state machine (ASM), Generic Array Logic (GAL), Hardware description language (HDL), Digital systems, States minimization, Verilog, HDL Control unit, in digital systems is one of the vital problems of optimal design. Several approaches of developing minimized modules for digital systems were studied. Algorithmic State Machine (ASM) has been analyzed by different approaches as coding the Excitation Function, coding the Input Logical Word and coding the Output Variables. This paper presents a modified method to synthesize the State Table (ST) of a digital system based on modifying the State Table Strings - rows. This new method results in minimizing the hardware used. Hardware Description Language (HDL) is the modern way for hardware design implementation, used in Programmable Logical Devices (PLD) such as Generic Array Logic (GAL) and Field-Programmable Gate Array (FPGA).The suggested method was tested and analyzed using Verilog HDL. July - September 2008 Copyright © 2008 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=242