JEE_V4_N3_RP2 Weibo Hu Donald Y.C. Lie Journal on Electrical Engineering 2230 – 7176 4 3 17 22 SAR ADC, DAC, Capacitor Switching Method A 10-bit single-ended ultra-low-power Successive Approximation Register ADC with a novel DAC switching technique is designed in the TSMC 0.18 micro metre mixed-signal CMOS technology. This method uses a reference voltage of V(R)/2, rather than V(R), as the only reference voltage to digitize the input signals with the amplitude range of [0, V(R)]. Compared with the conventional switching method, this work reduces the size of binary-weighted capacitor array by 50%, lowering the average power consumption in the DAC during digitizing by 87.5%, and it also reduces the power consumption during sampling by 63.5%. With the sampling frequency of 77 kHz, ADC's post-layout simulation resolution is 8.84 bits and ERBW (Effective Resolution Bandwidth) is 60 kHz, and the post-layout simulation FOM of our 10-bit SAR ADC can reach 18.9 fJ/(conversion-step), which is among the best ADCs FOM reported in a CMOS 0.18 micro metre technology. January - March 2011 Copyright © 2011 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=1395