FPGA Based Convolution Encoder Time Domain and State machine design Using VHDL

JDP_V2_N1_RP6 FPGA Based Convolution Encoder Time Domain and State machine design Using VHDL S.P. Kurlekar Journal on Digital Signal Processing 2322–0368 2 1 33 36 VHDL (VHSIC Hardware Description Language, FPGA (Field Programmable Gate Array) When the errors introduced by the information channel are unacceptable then the channel coding is needed. The use of channel coders with source coders provides the efficient and reliable transmission in the presence of noise. The use of channel coders with source coders provides the efficient and reliable transmission in the presence of noise. Coding permits an increased rate of information transfer at a fixed error rate, or a reduced error rate for a fixed transfer rate. A convolution coder accepts a fixed number of message symbols and produces a fixed number of code symbols, but its computations depends not only on the current set of input symbols but also on some of previous input symbols.[1] Through this paper we have illustrated design of convolution encoder using time domain approach with VHDL platform. The target technology is used as Sparten FPGA device. January - March 2014 Copyright © 2014 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=2723