JFET_V2_N4_RP4 S.R. Ruckmani P. Anbalagan Journal on Future Engineering and Technology 2230 – 7184 2 4 61 67 System-on-a-chip, power consumption, speed, hardware design, FPGA, fast prototyping, AMBA This paper introduces the main design principles and methods for asynchronous VLSI systems, with an emphasis on Advanced Microcontroller Bus Architecture (AMBA) communication. SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). The asynchronous design has been described and implemented to achieve high performance in comparison with the synchronous design. This implementation justifies the claimed performance through the Field Programmable Gate Array (FPGA) implementation results. Experimental results show that the techniques are indeed effective for IP development/verification and fast prototyping. This technique will reduce the power consumption and improve the speed by at least 50% without big impact on the system performance. May - July 2007 Copyright © 2007 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=806