JES_V3_N3_RP5 Raj Kumar Kante Thrimurthulu V. Journal on Embedded Systems 2278 - 7895 3 3 39 44 Sorting, Bit Wise and Operation, Verilog, RTL Description and Xilinx Virtex -5 Fpga Sorting is a deep-rooted problem in Computer Science and is a means of operation in quite a lot of applications. In this paper, the authors’ have proposed a complete VLSI model of sorting mechanism to find first maxima/minima values using (BWA) Bit Wise and Architecture. In this effort, a parallel radix-sort-based VLSI architecture for finding the first W maximum (or minimum) values is proposed. The described architecture, named Bit-Wise-And (BWA) architecture with an added advantage of high level scalability depends on analyzing input data from the most significant bit to the least significant one, the proposed scheme along with parallel structure has been modelled successfully on Xilinx Virtex -5 Fpga with a simple verilog RTL description. August - October 2014 Copyright © 2014 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=3299