JES_V2_N1_RP3 P. Hemanth Kumar G. Rajesh Journal on Embedded Systems 2278 - 7895 2 1 14 16 Flip Flop, Low Power, CMOS Circuit Low power flip-flops which play a vital role for the design of low-power digital systems. Flip flops and latches consume large amount of power due to redundant transitions and clocking system. In addition, the energy consumed by low skew clock distribution network is steadily increasing and becoming a larger fraction of the chip power. Almost, 30% -60% of total power dissipation in a system is due to flip flops and clock distribution network. In order to achieve a design that is both high performances while also being power efficient, careful attention must be paid to the design of flip flops and latches. The authors survey a set of flip flops designed for low power and High performance. February - April 2013 Copyright © 2013 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=2235