JES_V1_N1_Rev1 Jasmer Singh K.Saha G. L. Pahuja Journal on Embedded Systems 2278 - 7895 1 1 37 44 Low Power, Dynamic Threshold Voltage V(th) Scaling (DVTS), Dynamic Voltage Scaling (DVS), Dynamic Voltage and Frequency Scaling (DVFS), Razor Flip-Flop, Canary Flip-Flop, Error Detection, Error Correction IC Designers are struggling for tradeoff between significant variation effects and very tight power constraints in current nanometer regime. Usage of conventional timing safety margin approach becomes the cause of continuous power consumption to prevent the design from low probability timing variations. Various solutions have been proposed to achieve optimized power consumption/dissipation. Dynamic Threshold Voltage Vth Scaling (DVTS), Dynamic Voltage Scaling (DVS) and Dynamic Voltage and Frequency Scaling (DVFS) are some of the reported techniques in literature to achieve optimized power consumption. These approaches deals with aggressive standby Vth and VDD scaling by tracking PVT variations to smartly tradeoff between safety of data and decreased power consumption. In this paper different power saving strategies are discussed along with their benefits and limitations. This study will be helpful to select an effective power saving strategy to minimize the power dissipation. February - April 2012 Copyright © 2012 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=1736