jele.7.4.13686 Comparison of Different Designs of Pulse Triggered Flip-Flop based Shift Register at 32nm Technology Sandeep Kumar Khemraj Deshmukh Journal on Electronics Engineering 2249–0760 6 4 28 33 https://doi.org/10.26634/jele.7.4.13686 Pulse Triggered Flip-Flop, SISO Shift Register, Low Power, Clock Gating, Dynamic Power, 32nm Bulk CMOS In digital VLSI, sequential elements are most power consuming components. Flip-Flops are the basic storage elements and subsystem of clock distribution network which consume large amount of power. Nowadays for digital design, designers use pipelining techniques to design flip-flop based systems, such as shift registers and register files. In this paper, Pulse Triggered Flip-flop (P-FF) is discussed and Serial in Serial out (SISO) shift register is designed as its application. The main objective of this paper is to optimize the area and power of the shift register for use in Application Specific Integrated Circuits (ASICs) and embedded systems. This paper demonstrates the design of SISO shift registers in three different ways. First shift register is simple in structure and designed only by using P-FF. Second shift register uses clock gating circuit to reduce the switching power consumption and third design of shift register, pulse generator of P-FF is shared among all the latches. These three different SISO shift registers are compared in terms of power dissipation and transistor counts. Shift register has been designed at schematic level and simulated using Tanner EDA at CMOS 32nm BSIM4 technology. The simulation results of SISO shift register with common pulse generator shows effective reduction of power consumption and transistor count. June – August 2017 Copyright © 2017 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=13686