jele.7.4.13683 Analysis and Design of Body Driven Dynamic Latch based Comparator in Low Supply Voltages with nMOS Driver Vijay Savani N.M. Devashrayee Journal on Electronics Engineering 2249–0760 6 4 1 8 https://doi.org/10.26634/jele.7.4.13683 Dynamic Latch Comparator, Body Driven Comparator, Low Power, Low Supply Voltage, Power-Delay Analysis High speed operation, ultra-low power utilization, and efficiency are the need of battery operated handheld devices. This need forces the use of dynamic latch based comparator, having characteristics of using low supply voltage, high speed, and less power utilization. In this paper, the delay analysis of the body driven p-channel metal oxide semiconductor with a low voltage dynamic comparator is presented. The enhancement in the present structure as suggested by the previous work for fast operation in lower supply voltage is presented. Finally, the modification of the structure is proposed with the help of n-channel metal oxide semiconductor driver based design. Simulation results in 90 nm complementary metal oxide semiconductor technology are carried out for previous work and proposed design. The maximum clock frequency of the modified comparator topology can be achieved up to 500 MHz at a supply voltage of 1 V while consuming 67% less power compared to the previously reported topology. June – August 2017 Copyright © 2017 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=13683