JELE_V6_N3_RP2 Kondu Dharitha Reddy P.V. Mahesh Journal on Electronics Engineering 2249 – 0760 6 3 7 14 Architecture, Brent-Kung Adder, Vedic Mathematics, Vedic-Wallace (VW), Urdhava Tiryakbhyam Sutra, Arithmetic Logic Unit This paper is devoted to design a high-speed Arithmetic Logic Unit. All of us know that, ALU is a module which can perform arithmetic and logic operations. The speed of ALU greatly depends upon the speed of the Multiplier. This paper presents a technique called, “Vedic Mathematics” for designing the multiplier that is fast as compared to other multipliers based on mathematical techniques that have been in practice for a long time. Here, a high-speed 32x32 bit multiplier is designed and analyzed which is based on the Vedic mathematics mechanism. The proposed method is efficient and fast, wherein the processing involves the vertical and crossed multiplication of precedent Vedic mathematics. The internal multiplier is implemented using Vedic-Wallace structure for high-speed implementation. The exponent of the final result is obtained by using Brent-Kung adder for fast computations with less area utilization. The projected Vedic multiplier is coded in a High-level Digital Language (VHDL) followed by synthesization using an EDA tool, XilinxISE14.5. The proposed ALU is able to perform three different arithmetic and eight different logical operations at high speed. The main objective of this paper is to increase the speed of the multiplier and to decrease the delay, and area of the hardware. March – May 2016 Copyright © 2016 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=5954