JELE_V6_N1_RP2 S. Suvarna K. Rajesh S. Veerakumar Journal on Electronics Engineering 2249 – 0760 6 1 13 20 Negative Bias Temperature Instability (NBTI), Positive Bias Temperature Instability (PBTI), Radix-4, Modified Booth Encoding, Adaptive Hold Logic (AHL), Xilinx ISE Digital multipliers are most efficiently used in many applications such as Fourier Transform, Discrete Cosine Transforms, and Digital Filtering for high speed and low power consumption. The throughput of the multipliers is based on speed of the multiplier, and if it is too slow then, the entire performance of the circuit will be diminished. The pMOS transistor in negative bias cause Negative Bias Temperature Instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause Positive Bias Temperature Instability (PBTI). These effects reduce the transistor speed and the system may fail due to timing violations. So here, a new multiplier was designed with novel Adaptive Hold Logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), it is possible to reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit. September – November 2015 Copyright © 2015 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=3681