JELE_V4_N3_RP4 Devi Priya S. Lavanya Aswin Tilak A. Journal on Electronics Engineering 2249 – 0760 4 3 20 28 SRAM(Static Random Access Memory), GOBD(Gate Oxide Breakdown), HBD(Hard Breakdown), SBD(Soft Breakdown), BSIR(Built In Self Repair), PVT (Process, Voltage and Temperature) Scaling of the CMOS [Complementary Metal Oxide Semiconductor] technology associated with gate oxide thickness has become a major barrier for the design of circuit in nanoscale Static Random Access Memory (SRAM), especially in lower voltages. The operation of SRAM arrays are critical in reducing the power consumption. The Gate Oxide Breakdown caused by excessive electric field in the gate oxide causes increased vulnerability of the circuit performance, during breakdown. The devices are characterized by increased minimum voltage due to increase the static write failure as the voltage decreases. The design circuits were schematized using the DSCH2 schematic design tool, and their layouts were generated with the Micro wind 2 VLSI layout CAD tool. The proposed structures are simulated using Xilinx ISE design suite. March – May 2014 Copyright © 2014 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=2677