JELE_V4_N3_RP2 Balaji Morasa Keerthana Varun K. Journal on Electronics Engineering 2249 – 0760 4 3 9 13 CMOS [Complementary Metal Oxide Semiconductor], Scaling, Leakage Power, Power Dissipation, D Flip-flop, Ring Counter, Conventional Logic Gates, Schema Symbol, Dual Sleep Transistor Approach, Analog Simulation In CMOS [Complementary Metal Oxide Semiconductor] integrated circuits design, scaling is challenged by higher power consumption. The significant growth in power dissipation has occurred mainly due to the higher clock speeds in addition to the smaller process geometries. The transistor packaging density and functionality on a chip is improved by scaling. The speed and frequency of operation is increased due to scaling and hence higher performance is achieved. When the technology scales down, then the leakage current increases exponentially. In 90 nm and below technologies, leakage power constitutes 30-40% of total power dissipation. In this paper, a dual sleep transistor approach is used for reducing the power dissipation of ring counter circuit with minimum possible area. The simulations were done using Micro wind Layout Editor and DSCH [Digital Schematic Editor] software. March – May 2014 Copyright © 2014 i-manager publications. All rights reserved. i-manager Publications http://www.imanagerpublications.com/Article.aspx?ArticleId=2674